oSIST prEN IEC 63550-2:2025

SLOVENSKI STANDARD
01-november-2025
Polprevodniški elementi - Nevromorfne naprave - 2. del: Metoda ocenjevanja
linearnosti v memristorskih napravah
Semiconductor devices - Neuromorphic devices - Part 2: Evaluation method of linearity
in memristor devices
Dispositifs à semiconducteurs - Dispositifs neuromorphiques - Partie 2: Méthode
d’évaluation de la linéarité des dispositifs à memristance
Ta slovenski standard je istoveten z: prEN IEC 63550-2:2025
ICS:
31.080.99 Drugi polprevodniški elementi Other semiconductor devices
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

47/2942/CDV
COMMITTEE DRAFT FOR VOTE (CDV)

PROJECT NUMBER:
IEC 63550-2 ED1
DATE OF CIRCULATION: CLOSING DATE FOR VOTING:
2025-09-05 2025-11-28
SUPERSEDES DOCUMENTS:
47/2871/CD, 47/2926/CC
IEC TC 47 : SEMICONDUCTOR DEVICES
SECRETARIAT: SECRETARY:
Korea, Republic of Mr Cheolung Cha
OF INTEREST TO THE FOLLOWING COMMITTEES: HORIZONTAL FUNCTION(S):

ASPECTS CONCERNED:
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TITLE:
Semiconductor devices - Neuromorphic devices - Part 2: Evaluation method of
linearity in memristor devices

PROPOSED STABILITY DATE: 2029
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IEC CDV 63550-2 © IEC:2025
1 CONTENTS
3 FOREWORD . 4
4 1. Scope . 6
5 2. Normative references . 6
6 3. Terms and definitions . 6
7 4 Device under test (DUT) . 7
8 4.1 General . 7
9 5. Test apparatus and environment. 8
10 5.1 Test apparatus . 8
11 Overall system . 8
12 5.1.2 Semiconductor parameter analyzer . 8
13 5.1.3 Probe station . 8
14 5.2 Test environment . 9
15 6. Test method . 9
16 6.1 Long term potentiation (LTP) . 9
17 6.2 Long term depression (LTD) . 10
18 6.3 Linearity . 12
19 Mathematical evaluation for linearity and non-linearity factor in LTP and
20 LTD . 12
21 Linearity factor (ν) . 12
22 Non-linearity factor (NL) . 13
23 Weight update margin (ΔG) . 13
24 Retention . 13
25 7. Test Report . 16
26 Annex A 17
27 A.1 Measurement methods of LTP and LTD . 17
28 A.2 Evaluating the forgetting characteristics . 18
29 Bibliography . 19
31 Figure 1 – a) Schematic of memristor device. b) Equivalent circuit of a memristor
32 device . 7
33 Figure 2 – Block diagram of the measurement setup of a memristor device . 8
34 Figure 3 – Simulation test flow chart of the LTP operation of a memristor device . 10
35 Figure 4 – Simulation test flow chart of the LTD operation of a memristor device . 11
36 Figure 5 – Example of experimental LTP and LTD when input stimuli applied to the
37 memristor device . 11
38 Figure 6 – Simulation test flow chart of the linearity operation of a memristor device . 12
39 Figure 7 – Conductance-pulse graph showing synaptic weight update characteristics of
40 LTP and LTD. . 13
41 Figure 8 – Simulation test flow chart of the retention operation of a memristor device . 14
42 Figure 9 – Exemplary plot of retention characteristics of selected conductance states . 15
43 Figure A.1 –Gradual conductance modulation for LTP and LTD in the synaptic
44 electrical device. . 17
IEC CDV 63550-2 © IEC:2025
45 Figure A.2 – Forgetting behaviour curve and fitted curves of the electrical synapse
46 after consecutive programming pulses. . 18
IEC CDV 63550-2 © IEC:2025
INTERNATIONAL ELECTROTECHNICAL COMMISSION
50 ____________
53 Semiconductor devices - Neuromorphic devices -
55 Part 2: Evaluation method of linearity in memristor devices
FOREWORD
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94 not be held responsible for identifying any or all such patent rights.
International Standard IEC 63550-2-X has been prepared by technical committee 47:
Semiconductor devices.
The text of International Standard is based on the following documents:
NP Report on voting
47/XX/NP 47/XX/NP
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
IEC CDV 63550-2 © IEC:2025
The language used for the development of this International Standard is English.
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, and the
ISO/IEC Directives, JTC 1 Supplement available at www.iec.ch/members_experts/refdocs. The
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The committee has decided that the contents of this publication will remain unchanged until the
stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data related to
the specific publication. At this date, the publication will be
112 • reconfirmed,
113 • withdrawn,
114 • replaced by a revised edition, or
115 • amended.
IEC CDV 63550-2 © IEC:2025
117 Semiconductor devices - Neuromorphic devices -
119 Part 2: Evaluation method of linearity in memristor devices
1. Scope
This part of IEC 63550-2 specifies the test methods for evaluating the linearity of neuromorphic
memristor devices. The test methods in this international standard include long term
potentiation (LTP), long term depression (LTD), endurance and retention of LTD/LTP, and
linearity. This document is applicable to neuromorphic 2-teminal memristor devices without any
limitations prone to device technology and size.
2. Normative references
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies.
For undated references, the latest edition of the referenced document (including any
amendments) applies.
IEC 62951-9:2022 Semiconductor devices - Flexible and stretchable semiconductor devices
Part 9: Performance testing methods of one transistor and one resistor (1T1R) resistive memory
cells
3. Terms and definitions
For the purpose of this document, the following terms and definitions apply.
ISO and IEC maintain terminological databases for use in standardization at the following
addresses:
140 • IEC Electropedia: available at http://www.electropedia.org/
141 • ISO Online browsing platform: available at http://www.iso.org/obp
3.1
143 potentiation
increase in conductance (synaptic weights) depending on applied voltages over time [SOURCE:
IEC 63550-1:XXX,3.14]
3.2
147 depression
decrease in conductance (synaptic weights) depending on applied voltages over time [SOURCE:
IEC 63550-1:XXX,3.15]
3.3
potentiation voltage
152 V
Po
voltage required to increase the conductance of the memristor after forming process
3.4
155 depression voltage
156 V
De
voltage required to switch to decrease the conductance of the memristor
3.5
159 potentiation time
160 t
Po
time required to increase the conductance of memristor
IEC CDV 63550-2 © IEC:2025
3.6
163 depression time
164 tDe
time required to decrease the conductance of memristor
3.7
167 pulse interval
△t
time interval between the falling edge of the first pulse and the rising edge of the second pulse
of two consecutive pulses [SOURCE: IEC 63550-1:XXX,3.16]
171 synaptic weight
W
scalar value determining the influence of a presynaptic neuron on a postsynaptic neuron
[SOURCE: IEC 63550-1:XXX,3.17]
175 3.8
176 synaptic Plasticity
synaptic plasticity is a property dependent modification of the strength of synaptic weights by
stimuli [SOURCE: IEC 63550-1:XXX,3.18]
180 4 Device under test (DUT)
181 4.1 General
The equivalent circuit diagram and schematic structure of 2-terminal memristor devices (DUT)
is shown in Figure 1. The
...