29.045 - Semiconducting materials
ICS 29.045 Details
Semiconducting materials
Halbleitende Stoffe
Materiaux semi-conducteurs
Polprevodniški materiali
General Information
Frequently Asked Questions
ICS 29.045 is a classification code in the International Classification for Standards (ICS) system. It covers "Semiconducting materials". The ICS is a hierarchical classification system used to organize international, regional, and national standards, facilitating the search and identification of standards across different fields.
There are 154 standards classified under ICS 29.045 (Semiconducting materials). These standards are published by international and regional standardization bodies including ISO, IEC, CEN, CENELEC, and ETSI.
The International Classification for Standards (ICS) is a hierarchical classification system maintained by ISO to organize standards and related documents. It uses a three-level structure with field (2 digits), group (3 digits), and sub-group (2 digits) codes. The ICS helps users find standards by subject area and enables statistical analysis of standards development activities.
- Corrigendum3 pagesEnglish and French languagee-Library read for1 day
- Corrigendum3 pagesEnglish and French languagee-Library read for1 day
IEC 60146-1-1:2024 specifies the requirements for the performance of all semiconductor power converters and semiconductor power switches using controllable and/or non-controllable electronic valve devices. It is primarily intended to specify the basic requirements for converters in general and the requirements applicable to line commutated converters for conversion of AC power to DC power or vice versa. Parts of this document are also applicable to other types of electronic power converter provided that they do not have their own product standards.
This fifth edition introduces four main changes:
a) re-edition of the whole standard according to the current directives;
b) deletion of safety-related descriptions considering coordination with IEC 62477 series;
c) changes of calculation methods of inductive voltage regulation;
d) changes considering coordination with IEC 61378 series.
- Standard1 pageEnglish and French languagesale 15% off
IEC 60146-1-1:2024 specifies the requirements for the performance of all semiconductor power converters and semiconductor power switches using controllable and/or non-controllable electronic valve devices. It is primarily intended to specify the basic requirements for converters in general and the requirements applicable to line commutated converters for conversion of AC power to DC power or vice versa. Parts of this document are also applicable to other types of electronic power converter provided that they do not have their own product standards.
This fifth edition introduces four main changes:
a) re-edition of the whole standard according to the current directives;
b) deletion of safety-related descriptions considering coordination with IEC 62477 series;
c) changes of calculation methods of inductive voltage regulation;
d) changes considering coordination with IEC 61378 series.
- Standard92 pagesEnglish languagee-Library read for1 day
IEC 62899-203:2024 defines terms and specifies standard methods for characterization and evaluation of semiconductor inks and semiconductive layers that are made from semiconductor inks. This edition includes the following significant technical changes with respect to the previous edition:
a) addition of 6.3.1.2.2 - Normalised on-current measurement of the TFT device;
b) in 6.3.2, correction of formula for calculation of permittivity.
- Standard23 pagesEnglish languagesale 15% off
- Standard47 pagesEnglish languagesale 15% off
IEC 60146-1-1:2024 specifies the requirements for the performance of all semiconductor power converters and semiconductor power switches using controllable and/or non-controllable electronic valve devices. It is primarily intended to specify the basic requirements for converters in general and the requirements applicable to line commutated converters for conversion of AC power to DC power or vice versa. Parts of this document are also applicable to other types of electronic power converter provided that they do not have their own product standards. This fifth edition introduces four main changes: a) re-edition of the whole standard according to the current directives; b) deletion of safety-related descriptions considering coordination with IEC 62477 series; c) changes of calculation methods of inductive voltage regulation; d) changes considering coordination with IEC 61378 series.
- Standard92 pagesEnglish languagee-Library read for1 day
IEC 60146-1-1:2024 specifies the requirements for the performance of all semiconductor power converters and semiconductor power switches using controllable and/or non-controllable electronic valve devices. It is primarily intended to specify the basic requirements for converters in general and the requirements applicable to line commutated converters for conversion of AC power to DC power or vice versa. Parts of this document are also applicable to other types of electronic power converter provided that they do not have their own product standards.
This fifth edition introduces four main changes:
a) re-edition of the whole standard according to the current directives;
b) deletion of safety-related descriptions considering coordination with IEC 62477 series;
c) changes of calculation methods of inductive voltage regulation;
d) changes considering coordination with IEC 61378 series.
The content of the corrigendum 1 (2025-03) has been included in this copy.
- Standard295 pagesEnglish languagesale 15% off
- Standard182 pagesEnglish and French languagesale 15% off
SIGNIFICANCE AND USE
5.1 Electronic circuits used in many space, military, and nuclear power systems may be exposed to various levels and time profiles of neutron radiation. It is essential for the design and fabrication of such circuits that test methods be available that can determine the vulnerability or hardness (measure of survivability) of components to be used in them. A determination of hardness is often necessary for the short term (≈100 μs) as well as long term (permanent damage) following exposure. See Practice E722.
SCOPE
1.1 This guide defines the requirements and procedures for testing silicon discrete semiconductor devices and integrated circuits for rapid annealing effects from displacement damage resulting from neutron radiation. This test will produce degradation of the electrical properties of the irradiated devices and should be considered a destructive test. Rapid annealing of displacement damage is usually associated with bipolar technologies.
1.1.1 Heavy ion beams can also be used to characterize displacement damage annealing (1),2 but ion beams have significant complications in the interpretation of the resulting device behavior due to the associated ionizing dose. The use of pulsed ion beams as a source of displacement damage is not within the scope of this standard.
1.2 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard.
1.3 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety, health, and environmental practices and determine the applicability of regulatory limitations prior to use.
1.4 This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee.
- Guide7 pagesEnglish languagesale 15% off
SIGNIFICANCE AND USE
4.1 The electrical behavior of semiconducting extruded shielding materials is important for a variety of reasons, such as safety, static charges, and current transmission. This test method is useful in predicting the behavior of such semiconducting compounds. Also see Test Method D4496.
SCOPE
1.1 This test method covers the procedure for determining the volume resistivity, measured longitudinally, of extruded crosslinked and thermoplastic semiconducting, conductor and insulation shields for wire and cable.
1.2 In common practice the conductor shield is often referred to as the strand shield.
1.3 Technically, this test method is the measurement of a resistance between two electrodes on a single surface and modifying that value using dimensions of the specimen geometry to calculate a resistivity. However, the geometry of the specimen is such as to support the assumption of a current path primarily throughout the volume of the material between the electrodes, thus justifying the use of the term “longitudinal volume resistivity.” (See 3.1.2.1.)
1.4 Whenever two sets of values are presented, in different units, the values in the first set are the standard, while those in parentheses are for information only.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety, health, and environmental practices and determine the applicability of regulatory limitations prior to use. For a specific hazard statement, see 7.1.
1.6 This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee.
- Standard3 pagesEnglish languagesale 15% off
IEC 62899-503-3:2021(E) specifies a measuring method of contact resistance for printed thin film transistors (TFTs) by the transfer length method (TLM). The method requires the fabrication of a test element group (TEG) with varying channel length (L) between source and drain electrodes. The method is intended for quality assessment of TFT electrode contacts and is suited for determining whether the contact resistance lies within a desired range.
- Standard13 pagesEnglish languagesale 15% off
ABSTRACT
This specification covers extruded cross linked and thermoplastic semi-conducting, conductor and insulation shielding materials for electrical wires and cables. The materials covered are not compatible with hydro carbon derivatives of a swelling or deteriorating nature. Different tests shall be performed in order to determine physical properties like brittleness, aging requirements, and elongation at rupture and volume resistivity.
SCOPE
1.1 This specification covers crosslinked and thermoplastic extruded semi-conducting, conductor, and insulation shielding materials for electrical wires and cables.
1.2 In many instances, the electrical properties of the shielding material are strongly dependent on processing conditions. For this reason, in this specification the material is sampled from cable. Therefore, tests are done on shielded wire in this standard solely to determine the relevant property of the shielding material and not to test the conductor or completed cable.
1.3 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard.
1.4 This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee.
- Technical specification2 pagesEnglish languagesale 15% off
IEC 62899-503-1:2020(E) specifies a test method for displacement current measurement (DCM) for printed thin film transistors (TFTs) or organic thin film transistors (OTFTs).
- Standard15 pagesEnglish languagesale 15% off
SIGNIFICANCE AND USE
5.1 Although it would be desirable to measure the extent of profile distortion in any unknown sample by using a standard sample and this guide, measurements of interface width (profile distortion) can be unique to every sample composition (1, 2).4 This guide, describes a method that determines the unique width of a particular interface for the chosen set of operating conditions. It is intended to provide a method for checking on proper or consistent, or both, instrument performance. Periodic analysis of the same sample followed by a measurement of the interface width, in accordance with this guide, will provide these checks.
5.2 The procedure described in this guide is adaptable to any layered sample with an interface between layers in which a nominated element is present in one layer and absent from the other. It has been shown that for SIMS in particular (3, 4) and for surface analysis in general (5, 6), only rigorous calibration methods can determine accurate interface widths. Such procedures are prohibitively time-consuming. Therefore the interface width measurement obtained using the procedure described in this guide may contain significant systematic error (7). Therefore, this measure of interface width may have no relation to similar measures made with other methods. However, this does not diminish its use as a check on proper or consistent instrument performance, or both.
5.3 This guide can be used for both elemental and molecular depth profiles, provided that the materials have constant sputter rates throughout the depth of the overlayer, and minimal interlayer mixing is occurring. For more detailed information regarding measurements of interface widths during organic depth profiling, please see Mahoney (8).
SCOPE
1.1 This guide provides the SIMS analyst with a method for determining the width of interfaces from SIMS sputtering data obtained from analyses of layered specimens (both organic and inorganic). This guide does not apply to data obtained from analyses of specimens with thin markers or specimens without interfaces such as ion-implanted specimens.
1.2 This guide does not describe methods for the optimization of interface width or the optimization of depth resolution.
1.3 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety, health, and environmental practices and determine the applicability of regulatory limitations prior to use.
1.4 This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee.
- Guide3 pagesEnglish languagesale 15% off
IEC TR 60146-1-2:2019 gives guidance on variations to the specifications given in IEC 60146-1-1:2009 to enable the specification to be extended in a controlled form for special cases. Background information is also given on technical points, which facilitates the use of IEC 60146-1-1:2009. This technical report primarily covers line commutated converters and is not in itself a specification, except as regards certain auxiliary components, in so far as existing standards may not provide the necessary data. This fifth edition includes the following significant technical changes with respect to the previous edition:
a) addition of annexes concerning the applications of converter transformers and of fuses for overcurrent protection;
b) changes of calculation methods related the inductive voltage regulation and changes of description on transformer losses to be consistent with the latest transformer standards;
c) addition and updates of references based on the latest information.
- Technical report105 pagesEnglish languagesale 15% off
- Technical report215 pagesEnglish languagesale 15% off
IEC 62899-203:2018(E) defines terms and specifies standard methods for characterisation and evaluation. This document is applicable to semiconductor inks and semiconductive layers that are made from semiconductor inks.
- Standard22 pagesEnglish languagesale 15% off
IEC/TR 62572-4:2013(E) which is a technical report, provides guidelines for optical connector end-face cleaning methods for receptacle style optical transceivers. It includes details about handling receptacle style optical transceivers, internal structures of optical transceivers, information on cleaning tools and machines, applicable cleaning methods and cleaning procedures. Receptacle style optical transceivers as well as optical fibre patch cords are handled by operators and maintenance staff of optical network systems. This technical report may be used as a guideline to prepare instruction manuals for the operators and maintenance staff of optical network systems. Keywords: optical connector end-face cleaning methods, receptacle style optical transceivers, optical network systems.
- Technical report23 pagesEnglish languagesale 15% off
- Technical report23 pagesEnglish languagesale 15% off
IEC 60146-1-1:2009 specifies the requirements for the performance of all semiconductor power converters and semiconductor power switches using controllable and/or non-controllable electronic valve devices. It is primarily intended to specify the basic requirements for converters in general and the requirements applicable to line commutated converters for conversion of a.c. power to d.c. power or vice versa. Parts of this standard are also applicable to other types of electronic power converter provided that they do not have their own product standards. This fourth edition constitutes a technical revision and introduces five main changes: - re-edition of the whole standard according to the current directives; - correction of definitions and addition of new terms, especially terms concerning EMC, harmonic distortion and insulation co-ordination; - the service condition tolerances have been revised according to the IEC 61000 series; - the insulation tests have been revised considering the insulation co-ordination; - addition of three annexes.
- Standard99 pagesEnglish languagee-Library read for1 day
IEC 60146-1-2:2011(E) gives guidance on variations to the specifications given in IEC 60146-1-1:2009 to enable the specification to be extended in a controlled form for special cases. Background information is also given on technical points which should facilitate the use of IEC 60146-1-1:2009. This technical report primarily covers line commutated converters and is not in itself a specification, except as regards certain auxiliary components, in so far as existing standards may not provide the necessary data. This fourth edition includes the following main changes with respect to the previous edition:
a) re-edition of the whole document according to the current Directives;
b) correction of some errors.
- Technical report83 pagesEnglish languagesale 15% off
IEC 60146-1-1:2009 specifies the requirements for the performance of all semiconductor power converters and semiconductor power switches using controllable and/or non-controllable electronic valve devices. It is primarily intended to specify the basic requirements for converters in general and the requirements applicable to line commutated converters for conversion of a.c. power to d.c. power or vice versa. Parts of this standard are also applicable to other types of electronic power converter provided that they do not have their own product standards. This fourth edition constitutes a technical revision and introduces five main changes:
- re-edition of the whole standard according to the current directives;
- correction of definitions and addition of new terms, especially terms concerning EMC, harmonic distortion and insulation co-ordination;
- the service condition tolerances have been revised according to the IEC 61000 series;
- the insulation tests have been revised considering the insulation co-ordination;
- addition of three annexes.
- Standard189 pagesEnglish and French languagesale 15% off
Specifies the requirements for the performance of all electronic power convertors and electronic power switches using controllable and/or non-controllable electronic valves. Specifies the requirements applicable to line commutated convertors for conversion of a.c. power to d.c. power or vice versa including tests and service conditions which influence the basis of rating. The contents of the corrigendum of August 1993 have been included in this copy.
- Standard10 pagesEnglish and French languagesale 15% off
SIGNIFICANCE AND USE
4.1 The electrical behavior of semiconducting extruded shielding materials is important for a variety of reasons, such as safety, static charges, and current transmission. This test method is useful in predicting the behavior of such semiconducting compounds. Also see Test Method D4496.
SCOPE
1.1 This test method covers the procedure for determining the volume resistivity, measured longitudinally, of extruded crosslinked and thermoplastic semiconducting, conductor and insulation shields for wire and cable.
1.2 In common practice the conductor shield is often referred to as the strand shield.
1.3 Technically, this test method is the measurement of a resistance between two electrodes on a single surface and modifying that value using dimensions of the specimen geometry to calculate a resistivity. However, the geometry of the specimen is such as to support the assumption of a current path primarily throughout the volume of the material between the electrodes, thus justifying the use of the term “longitudinal volume resistivity.” (See 3.1.2.1.)
1.4 Whenever two sets of values are presented, in different units, the values in the first set are the standard, while those in parentheses are for information only.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety, health, and environmental practices and determine the applicability of regulatory limitations prior to use. For a specific hazard statement, see 7.1.
1.6 This international standard was developed in accordance with internationally recognized principles on standardization established in the Decision on Principles for the Development of International Standards, Guides and Recommendations issued by the World Trade Organization Technical Barriers to Trade (TBT) Committee.
- Standard4 pagesEnglish languagesale 15% off
- Standard4 pagesEnglish languagesale 15% off
SIGNIFICANCE AND USE
5.1 Electronic circuits used in many space, military, and nuclear power systems may be exposed to various levels and time profiles of neutron radiation. It is essential for the design and fabrication of such circuits that test methods be available that can determine the vulnerability or hardness (measure of survivability) of components to be used in them. A determination of hardness is often necessary for the short term (≈100 μs) as well as long term (permanent damage) following exposure. See Practice E722.
SCOPE
1.1 This guide defines the requirements and procedures for testing silicon discrete semiconductor devices and integrated circuits for rapid-annealing effects from displacement damage resulting from neutron radiation. This test will produce degradation of the electrical properties of the irradiated devices and should be considered a destructive test. Rapid annealing of displacement damage is usually associated with bipolar technologies.
1.1.1 Heavy ion beams can also be used to characterize displacement damage annealing (1)2, but ion beams have significant complications in the interpretation of the resulting device behavior due to the associated ionizing dose. The use of pulsed ion beams as a source of displacement damage is not within the scope of this standard.
1.2 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard.
1.3 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to consult and establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
- Guide7 pagesEnglish languagesale 15% off
- Guide7 pagesEnglish languagesale 15% off
- Guide7 pagesEnglish languagesale 15% off
SIGNIFICANCE AND USE
4.1 In order to choose the proper material for producing semiconductor devices, knowledge of material properties such as resistivity, Hall coefficient, and Hall mobility is useful. Under certain conditions, as outlined in the Appendix, other useful quantities for materials specification, including the charge carrier density and the drift mobility, can be inferred.
SCOPE
1.1 These test methods cover two procedures for measuring the resistivity and Hall coefficient of single-crystal semiconductor specimens. These test methods differ most substantially in their test specimen requirements.
1.1.1 Test Method A, van der Pauw (1) 2—This test method requires a singly connected test specimen (without any isolated holes), homogeneous in thickness, but of arbitrary shape. The contacts must be sufficiently small and located at the periphery of the specimen. The measurement is most easily interpreted for an isotropic semiconductor whose conduction is dominated by a single type of carrier.
1.1.2 Test Method B, Parallelepiped or Bridge-Type—This test method requires a specimen homogeneous in thickness and of specified shape. Contact requirements are specified for both the parallelepiped and bridge geometries. These test specimen geometries are desirable for anisotropic semiconductors for which the measured parameters depend on the direction of current flow. The test method is also most easily interpreted when conduction is dominated by a single type of carrier.
1.2 These test methods do not provide procedures for shaping, cleaning, or contacting specimens; however, a procedure for verifying contact quality is given.
Note 1: Practice F418 covers the preparation of gallium arsenide phosphide specimens.
1.3 The method in Practice F418 does not provide an interpretation of the results in terms of basic semiconductor properties (for example, majority and minority carrier mobilities and densities). Some general guidance, applicable to certain semiconductors and temperature ranges, is provided in the Appendix. For the most part, however, the interpretation is left to the user.
1.4 Interlaboratory tests of these test methods (Section 19) have been conducted only over a limited range of resistivities and for the semiconductors, germanium, silicon, and gallium arsenide. However, the method is applicable to other semiconductors provided suitable specimen preparation and contacting procedures are known. The resistivity range over which the method is applicable is limited by the test specimen geometry and instrumentation sensitivity.
1.5 The values stated in acceptable metric units are to be regarded as the standard. The values given in parentheses are for information only. (See also 3.1.4.)
1.6 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
- Standard14 pagesEnglish languagesale 15% off
- Standard14 pagesEnglish languagesale 15% off
ABSTRACT
This specification covers extruded cross linked and thermoplastic semi-conducting, conductor and insulation shielding materials for electrical wires and cables. The materials covered are not compatible with hydro carbon derivatives of a swelling or deteriorating nature. Different tests shall be performed in order to determine physical properties like brittleness, aging requirements, and elongation at rupture and volume resistivity.
SCOPE
1.1 This specification covers crosslinked and thermoplastic extruded semi-conducting, conductor and insulation shielding materials for electrical wires and cables.
1.2 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard.
1.3 In many instances, the electrical properties of the shielding material are strongly dependent on processing conditions. For this reason, in this specification the material is sampled from cable. Therefore, tests are done on shielded wire in this standard solely to determine the relevant property of the shielding material and not to test the conductor or completed cable.
- Technical specification2 pagesEnglish languagesale 15% off
SIGNIFICANCE AND USE
4.1 The electrical behavior of semiconducting extruded shielding materials is important for a variety of reasons, such as safety, static charges, and current transmission. This test method is useful in predicting the behavior of such semiconducting compounds. Also see Test Method D4496.
SCOPE
1.1 This test method covers the procedure for determining the volume resistivity, measured longitudinally, of extruded crosslinked and thermoplastic semiconducting, conductor and insulation shields for wire and cable.
1.2 In common practice the conductor shield is often referred to as the strand shield.
1.3 Technically, this test method is the measurement of a resistance between two electrodes on a single surface and modifying that value using dimensions of the specimen geometry to calculate a resistivity. However, the geometry of the specimen is such as to support the assumption of a current path primarily throughout the volume of the material between the electrodes, thus justifying the use of the term “longitudinal volume resistivity.” (See 3.1.2.1)
1.4 Whenever two sets of values are presented, in different units, the values in the first set are the standard, while those in parentheses are for information only.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use. For a specific hazard statement, see 7.1.
- Standard3 pagesEnglish languagesale 15% off
- Standard3 pagesEnglish languagesale 15% off
SIGNIFICANCE AND USE
Although it would be desirable to measure the extent of profile distortion in any unknown sample by using a standard sample and this guide, measurements of interface width (profile distortion) can be unique to every sample composition (1, 2, 3).3 This guide, that describes a method that determines the unique width of a particular interface for the chosen set of operating conditions. It is primarily intended to provide a method for checking on proper or consistent, or both, instrument performance. Periodic analysis of the same sample followed by a measurement of the interface width, in accordance with this guide, will provide these checks.
The procedure described in this guide is adaptable to any layered sample with an interface between layers in which a nominated element is present in one layer and absent from the other. It has been shown that for SIMS in particular (4, 5) and for surface analysis in general (6, 7), only rigorous calibration methods can determine accurate interface widths. Such procedures are prohibitively time-consuming. Therefore the interface width measurement obtained using the procedure described in this guide may contain significant systematic error (8). Therefore, this measure of interface width may have no relation to similar measures made with other methods. However, this does not diminish its use as a check on proper or consistent instrument performance, or both.
SCOPE
1.1 This guide provides the SIMS analyst with a method for determining the width of interfaces from SIMS sputtering data obtained from analyses of layered specimens. This guide does not apply to data obtained from analyses of specimens with thin markers or specimens without interfaces such as ion-implanted specimens.
1.2 This guide does not describe methods for the optimization of interface width or the optimization of depth resolution.
This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
- Guide3 pagesEnglish languagesale 15% off
- Guide3 pagesEnglish languagesale 15% off
SIGNIFICANCE AND USE
5.1 Electronic circuits used in many space, military, and nuclear power systems may be exposed to various levels and time profiles of neutron radiation. It is essential for the design and fabrication of such circuits that test methods be available that can determine the vulnerability or hardness (measure of nonvulnerability) of components to be used in them. A determination of hardness is often necessary for the short term (≈100 μs) as well as long term (permanent damage) following exposure. See Practice E722.
SCOPE
1.1 This guide defines the requirements and procedures for testing silicon discrete semiconductor devices and integrated circuits for rapid-annealing effects from displacement damage resulting from neutron radiation. This test will produce degradation of the electrical properties of the irradiated devices and should be considered a destructive test. Rapid annealing of displacement damage is usually associated with bipolar technologies.
1.1.1 Heavy ion beams can also be used to characterize displacement damage annealing (1)2, but ion beams have significant complications in the interpretation of the resulting device behavior due to the associated ionizing dose. The use of pulsed ion beams as a source of displacement damage is not within the scope of this standard.
1.2 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard.
1.3 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to consult and establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
- Guide7 pagesEnglish languagesale 15% off
- Guide7 pagesEnglish languagesale 15% off
SIGNIFICANCE AND USE
In order to choose the proper material for producing semiconductor devices, knowledge of material properties such as resistivity, Hall coefficient, and Hall mobility is useful. Under certain conditions, as outlined in the Appendix, other useful quantities for materials specification, including the charge carrier density and the drift mobility, can be inferred.
SCOPE
1.1 These test methods cover two procedures for measuring the resistivity and Hall coefficient of single-crystal semiconductor specimens. These test methods differ most substantially in their test specimen requirements.
1.1.1 Test Method A, van der Pauw (1) —This test method requires a singly connected test specimen (without any isolated holes), homogeneous in thickness, but of arbitrary shape. The contacts must be sufficiently small and located at the periphery of the specimen. The measurement is most easily interpreted for an isotropic semiconductor whose conduction is dominated by a single type of carrier.
1.1.2 Test Method B, Parallelepiped or Bridge-Type—This test method requires a specimen homogeneous in thickness and of specified shape. Contact requirements are specified for both the parallelepiped and bridge geometries. These test specimen geometries are desirable for anisotropic semiconductors for which the measured parameters depend on the direction of current flow. The test method is also most easily interpreted when conduction is dominated by a single type of carrier.
1.2 These test methods do not provide procedures for shaping, cleaning, or contacting specimens; however, a procedure for verifying contact quality is given.
Note 1—Practice F 418 covers the preparation of gallium arsenide phosphide specimens.
1.3 The method in Practice F 418 does not provide an interpretation of the results in terms of basic semiconductor properties (for example, majority and minority carrier mobilities and densities). Some general guidance, applicable to certain semiconductors and temperature ranges, is provided in the Appendix. For the most part, however, the interpretation is left to the user.
1.4 Interlaboratory tests of these test methods (Section 19) have been conducted only over a limited range of resistivities and for the semiconductors, germanium, silicon, and gallium arsenide. However, the method is applicable to other semiconductors provided suitable specimen preparation and contacting procedures are known. The resistivity range over which the method is applicable is limited by the test specimen geometry and instrumentation sensitivity.
1.5 The values stated in acceptable metric units are to be regarded as the standard. The values given in parentheses are for information only. (See also 3.1.4.)
1.6 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
- Standard14 pagesEnglish languagesale 15% off
- Standard14 pagesEnglish languagesale 15% off
SIGNIFICANCE AND USE
Solid-state electronic devices subjected to stresses from excessive current pulses sometimes fail because a portion of the metallization fuses or vaporizes (suffers burnout). Burnout susceptibility can vary significantly from component to component on a given wafer, regardless of design. This practice provides a procedure for establishing the limits of pulse current overstress within which the metallization of a given device should survive.
This practice can be used as a destructive test in a lot-sampling program to determine the boundaries of the safe operating region having desired survival probabilities and statistical confidence levels when appropriate sample quantities and statistical analyses are used.
Note 2—The practice may be extended to infer the survivability of untested metallization adjacent to the specimen metallization on a semiconductor die or wafer if care is taken that appropriate similarities exist in the design and fabrication variables.
SCOPE
1.1 This practice covers procedures for determining operating regions that are safe from metallization burnout induced by current pulses of less than 1-s duration.
Note 1—In this practice, “metallization” refers to metallic layers on semiconductor components such as interconnect patterns on integrated circuits. The principles of the practice may, however, be extended to nearly any current-carrying path. The term “burnout” refers to either fusing or vaporization.
1.2 This practice is based on the application of unipolar rectangular current test pulses. An extrapolation technique is specified for mapping safe operating regions in the pulse-amplitude versus pulse-duration plane. A procedure is provided in Appendix X2 to relate safe operating regions established from rectangular pulse data to safe operating regions for arbitrary pulse shapes.
1.3 This practice is not intended to apply to metallization damage mechanisms other than fusing or vaporization induced by current pulses and, in particular, is not intended to apply to long-term mechanisms, such as metal migration.
1.4 This practice is not intended to determine the nature of any defect causing failure.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
- Standard5 pagesEnglish languagesale 15% off
ABSTRACT
This specification covers extruded cross linked and thermoplastic semi-conducting, conductor and insulation shielding materials for electrical wires and cables. The materials covered are not compatible with hydro carbon derivatives of a swelling or deteriorating nature. Different tests shall be performed in order to determine physical properties like brittleness, aging requirements, and elongation at rupture and volume resistivity.
SCOPE
1.1 This specification covers crosslinked and thermoplastic extruded semi-conducting, conductor and insulation shielding materials for electrical wires and cables.
1.2 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard.
1.3 In many instances, the electrical properties of the shielding material are strongly dependent on processing conditions. For this reason, in this specification the material is sampled from cable. Therefore, tests are done on shielded wire in this standard solely to determine the relevant property of the shielding material and not to test the conductor or completed cable.
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ABSTRACT
This guide covers sputtering targets used as thin film source material in fabricating semiconductor electronic devices. It should be used to develop target specifications for specific materials. This standard sets purity grade levels, analytical methods and impurity content reporting method and format. The grade designation is a measure of total metallic impurity content. It does not necessarily indicate suitability for a particular application because factors other than total metallic impurity may influence performance. Analysis for trace metallic impurities and gases shall be performed on samples that represent the finished sputtering target. Carbon, oxygen, and sulfur shall be analysed by fusion and gas extraction/infrared spectroscopy. Nitrogen and hydrogen shall be analysed by fusion and gas extraction.
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1.1 This guide covers sputtering targets used as thin film source material in fabricating semiconductor electronic devices. It should be used to develop target specifications for specific materials and should be referenced therein.
1.2 This standard sets purity grade levels, analytical methods and impurity content reporting method and format.
1.2.1 The grade designation is a measure of total metallic impurity content. The grade designation does not necessarily indicate suitability for a particular application because factors other than total metallic impurity may influence performance.
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SIGNIFICANCE AND USE
Although it would be desirable to measure the extent of profile distortion in any unknown sample by using a standard sample and this guide, measurements of interface width (profile distortion) can be unique to every sample composition (1, 2, 3).3 This guide, that describes a method that determines the unique width of a particular interface for the chosen set of operating conditions. It is primarily intended to provide a method for checking on proper or consistent, or both, instrument performance. Periodic analysis of the same sample followed by a measurement of the interface width, in accordance with this guide, will provide these checks.
The procedure described in this guide is adaptable to any layered sample with an interface between layers in which a nominated element is present in one layer and absent from the other. It has been shown that for SIMS in particular (4, 5) and for surface analysis in general (6, 7), only rigorous calibration methods can determine accurate interface widths. Such procedures are prohibitively time-consuming. Therefore the interface width measurement obtained using the procedure described in this guide may contain significant systematic error (8). Therefore, this measure of interface width may have no relation to similar measures made with other methods. However, this does not diminish its use as a check on proper or consistent instrument performance, or both.
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1.1 This guide provides the SIMS analyst with a method for determining the width of interfaces from SIMS sputtering data obtained from analyses of layered specimens. This guide does not apply to data obtained from analyses of specimens with thin markers or specimens without interfaces such as ion-implanted specimens.
1.2 This guide does not describe methods for the optimization of interface width or the optimization of depth resolution.
This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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SIGNIFICANCE AND USE
The electrical behavior of semiconducting extruded shielding materials is important for a variety of reasons, such as safety, static charges, and current transmission. This test method is useful in predicting the behavior of such semiconducting compounds. Also see Test Method D 4496.
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1.1 This test method covers the procedure for determining the volume resistivity, measured longitudinally, of extruded crosslinked and thermoplastic semiconducting, conductor and insulation shields for wire and cable.
1.2 Whenever two sets of values are presented, in different units, the values in the first set are the standard, while those in parentheses are for information only.
This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use. For a specific hazard statement, see .
1.3 In common practice the conductor shield is often referred to as the strand shield.
1.4 Technically, this test method is the measurement of a resistance between two electrodes on a single surface and modifying that value using dimensions of the specimen geometry to calculate a resistivity. However, the geometry of the specimen is such as to support the assumption of a current path primarily throughout the volume of the material between the electrodes, thus justifying the use of the term "longitudinal volume resistivity." ( See 3.1.2.1 )
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1.1 This test method covers the procedure for determining the volume resistivity, measured longitudinally, of extruded crosslinked and thermoplastic semiconducting, conductor and insulation shields for wire and cable.
1.2 Whenever two sets of values are presented, in different units, the values in the first set are the standard, while those in parentheses are for information only.
This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use. For a specific hazard statement, see .
1.3 In common practice the conductor shield is often referred to as the strand shield.
1.4 While technically the volume resistivity in this test method is a longitudinal measurement of volume resistivity, in the wire and cable industry the word longitudinal is not used. This longitudinal measurement of volume resistivity will be referred to as "volume resistivity" throughout this standard.
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1.1 This test method covers the direct measurement of the sheet resistance and its variation for all but the periphery (amounting to three probe separations) for circular conducting layers pertinent to silicon semiconductor technology. These layers may be fabricated on substrates of any diameter that is capable of being securely mounted on a prober stage.
Note 1—The equation used to calculate the sheet resistance data from measurements is not perfectly accurate out to the edge of the wafer for probes oriented at an arbitrary angle with respect to a wafer radius. Further, automatic instruments on which this test method will be performed may not have perfect centering of the wafer on the measurement stage. These factors require that the periphery of the layer being measured be excluded. Also, many thin film processes use wafer clamps that preclude forming layers out to the edge of the substrate. The edge exclusion in this test method applies to the film that is being measured, rather than to the substrate. The equation used is based on mathematics developed for layers of circular shape. It is expected to work well for layers of other shapes such as rectangular, if edge exclusion requirements are met; however, the accuracy near the edge of other shapes has not been demonstrated (2).
1.2 This test method is intended primarily for assessing the uniformity of layers formed by diffusion, epitaxy, ion implant and chemical vapor, or other deposition processes on a silicon substrate. The deposited film, which may be single crystal, polycrystalline or amorphous silicon, or a metal film, must be electrically isolated from the substrate. This can be accomplished if the layer is of opposite conductivity type from the substrate or is deposited over a dielectric layer such as silicon dioxide. This test method is capable of measuring films as thin as 0.05 m, but particular care is required for establishing reliable measurements for most films in the range below 0.2 m. Films that have a thickness up to half the probe separation can be measured without the use of a thickness-related correction factor. It may give misleading results for films formed by silicon on insulator technologies because of charge or charge trapping in the insulator.
1.3 This test method can be used to measure the sheet resistance uniformity of bulk substrates. However, the thickness of the substrate must be known to be constant or must be measured at all positions where sheet resistance values are measured in order to calculate relative variations in resistance reliably.
Note 2—The thickness correction factor for layers that are thicker than 0.5 times the probe spacing is known to vary more rapidly than that for single-configuration four-probe measurements, but such a correction has not yet been published. Until such a correction is published, resistivity values determined by the dual-configuration method will not be accurate for these thicker specimens; however, if the wafer has uniform thickness, variations of resistivity can still be determined by this test method.
1.4 This test method can be used to measure sheet resistance values from below 10 m for metal films, to over 25 000 for thin silicon films. However, for films at the upper end of this resistance range, and for films toward the low end of the thickness range, the interpretation of the sheet resistance values may not be straightforward due to various semiconductor effects (3, 4, 5).
Note 3—The principles of this test method are also applicable to other semiconductor materials, but the appropriate conditions and the expected precision have not been established.
1.5 This test method uses two different electrical configurations of the four-point probe at each measurement location. It does not require measurement of probe location on the wafer, or probe separations, or of wafer diameter (except to determine edge exclusion for measurement-site selection) as do other four-point probe methods...
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1.1 This specification covers extruded crosslinked and thermoplastic semi-conducting, conductor and insulation shielding materials for electrical wires and cables.
1.2 The materials covered are not compatible with hydrocarbon derivatives of a swelling or deteriorating nature.
1.3 Whenever two sets of values are presented, in different units, the values in the first set are the standard, while those in parentheses are for information only.
1.4 In many instances, the electrical properties of the shielding material are strongly dependent on processing conditions. For this reason, in this specification the material is sampled from cable. Therefore, tests are done on shielded wire in this standard solely to determine the relevant property of the shielding material and not to test the conductor or completed cable.
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1.1 This specification covers extruded crosslinked and thermoplastic semi-conducting, conductor and insulation shielding materials for electrical wires and cables.
1.2 The materials covered are not compatible with hydrocarbon derivatives of a swelling or deteriorating nature.
1.3 Whenever two sets of values are presented, in different units, the values in the first set are the standard, while those in parentheses are for information only.
1.4 In many instances, the electrical properties of the shielding material are strongly dependent on processing conditions. For this reason, in this specification the material is sampled from cable. Therefore, tests are done on shielded wire in this standard solely to determine the relevant property of the shielding material and not to test the conductor or completed cable.
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1.1 This test method covers measurement of the thickness of silicon wafers, polished or unpolished, and estimation of the variation in thickness across the wafer.
1.2 This test method is intended primarily for use with wafers that meet the dimension and tolerance requirements of SEMI Specifications M1. However, it can be applied to circular silicon wafers, or substrates of any diameter and thickness that can be handled without breaking.
1.3 This test method is suitable for both contact and contactless gaging equipment. Precision statements have been established for each.
1.4 The values stated in inch-pound units are to be regarded as standard. The values in parentheses are for information only.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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1.1 This test method covers test site selection and data reduction procedures for radial variation of the interstitial oxygen concentration in silicon slices typically used in the manufacture of microelectronic semiconductor devices.
1.2 This test method is intended as both a referee and production test through selection of an appropriate test position plan.
1.3 The interstitial oxygen content may be measured in accordance with Test Methods F 1188 or F 1619, DIN 50438/1, JEIDA 61, or any other procedure agreed upon by the parties to the test.
Note 1—Test Method F 1366 is not based on infrared absorption measurement and it measures total oxygen content, not interstitial oxygen content. It is also a destructive technique. However, it can be used to determine the radial variation of the oxygen content if suitable modifications of the test procedure are made.
1.4 Acceptable thickness and surface finish for the test specimens are specified in the applicable test methods. This test method is suitable for use on chemically etched, single-side polished and double-side polished silicon wafers or slices with no surface defects that could adversely change infrared radiation transmission through the test specimen (subsequently called slice), provided that appropriate test methods for oxygen content are selected.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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1.1 This test method covers measurement of the thickness of silicon wafers, polished or unpolished, and estimation of the variation in thickness across the wafer.
1.2 This test method is intended primarily for use with wafers that meet the dimension and tolerance requirements of SEMI Specifications M1. However, it can be applied to circular silicon wafers, or substrates of any diameter and thickness that can be handled without breaking.
1.3 This test method is suitable for both contact and contactless gaging equipment. Precision statements have been established for each.
1.4 The values stated in inch-pound units are to be regarded as standard. The values in parentheses are for information only.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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1.1 This test method covers determination of the average amount of bow of nominally circular silicon wafers, polished or unpolished, in the free (non-clamped) condition.
1.2 This test method is intended primarily for use with wafers that meet the dimension and tolerance requirements of SEMI Specifications M1.
1.3 This test method can also be applied to circular wafers of other semiconducting materials, such as gallium arsenide, or electronic substrate materials, such as sapphire or gadolinium gallium garnet, that have a diameter of 25 mm or greater, a thickness of 0.18 mm or greater, and a ratio of diameter to thickness up to 250. Wafers to be tested may have one or more fiducial flats provided they are located in such a way that the slice can be centered on the support pedestals (see 7.1.2) without falling off.
1.4 The values stated in inch-pound units are to be regarded as the standard. The values given in parentheses are for information only.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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1.1 This test method covers a nondestructive procedure to determine whether or not the dimensions of fiducial notches on silicon wafers fall within specified limits.
1.2 The values stated in SI units are to be regarded as the standard. The values given in parentheses are for information only.
1.3 This standard does not purport to address all of the safety problems, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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1.1 This test method covers determination of the average amount of bow of nominally circular silicon wafers, polished or unpolished, in the free (non-clamped) condition.
1.2 This test method is intended primarily for use with wafers that meet the dimension and tolerance requirements of SEMI Specifications M1.
1.3 This test method can also be applied to circular wafers of other semiconducting materials, such as gallium arsenide, or electronic substrate materials, such as sapphire or gadolinium gallium garnet, that have a diameter of 25 mm or greater, a thickness of 0.18 mm or greater, and a ratio of diameter to thickness up to 250. Wafers to be tested may have one or more fiducial flats provided they are located in such a way that the slice can be centered on the support pedestals (see 7.1.2) without falling off.
1.4 The values stated in inch-pound units are to be regarded as the standard. The values given in parentheses are for information only.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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1.1 These test methods cover complementary procedures for testing the oxygen precipitation characteristics of silicon wafers. It is assumed that the precipitation characteristics are related to the amount of interstitial oxygen lost during specified thermal cycles.
1.2 These test methods may be used to compare qualitatively the precipitation characteristics of two or more groups of wafers.
1.3 These test methods may be applied to any - or -type, any orientation Czochralski silicon wafers whose thickness, resistivity, and surface finish are such as to permit the oxygen concentration to be determined by infrared absorption and whose oxygen concentration is such as to produce measurable oxygen loss.
1.4 These test methods are not suitable for determining the width or characteristics of a "denuded zone," a region near the surface of a wafer that is essentially free of oxide precipitates.
1.5 Because these test methods are destructive, suitable sampling techniques must be employed.
1.6 The values stated in SI units are regarded as standard.
1.7 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use. Specific hazard statements are given in Section 8.
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1.1 These test methods provide means for examining the edge contour of circular wafers of silicon, gallium arsenide, and other electronic materials, and determining fit to limits of contour specified by a template that defines a permitted zone through which the contour must pass. Principal application of such a template is intended for, but not limited to, wafers that have been deliberately edge shaped.
1.2 Two test methods are described. One is destructive and is limited to inspection of discrete points on the periphery, including flats. The contour of deliberately edge-shaped wafers may not be uniform around the entire periphery, and thus the discrete location(s) may or may not be representative of the entire periphery. The other test method is nondestructive and suitable for inspection of all points on the wafers periphery except flats.
1.3 The nondestructive test method may also be applied to the examination of the edge contour of the outer periphery of substrates for rigid disks used for magnetic storage of data.
Note 1—Reference to wafers in the remainder of this standard shall be interpreted to include substrates for rigid disks unless the phrase "of electronic materials" is also included in the context.
1.4 The values stated in SI units are to be regarded as the standard. The values given in parentheses are for information only.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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1.1 This test method covers test site selection and data reduction procedures for radial variation of the interstitial oxygen concentration in silicon slices typically used in the manufacture of microelectronic semiconductor devices.
1.2 This test method is intended as both a referee and production test through selection of an appropriate test position plan.
1.3 The interstitial oxygen content may be measured in accordance with Test Methods F 1188 or F 1619, DIN 50438/1, JEIDA 61, or any other procedure agreed upon by the parties to the test.
Note 1—Test Method F 1366 is not based on infrared absorption measurement and it measures total oxygen content, not interstitial oxygen content. It is also a destructive technique. However, it can be used to determine the radial variation of the oxygen content if suitable modifications of the test procedure are made.
1.4 Acceptable thickness and surface finish for the test specimens are specified in the applicable test methods. This test method is suitable for use on chemically etched, single-side polished and double-side polished silicon wafers or slices with no surface defects that could adversely change infrared radiation transmission through the test specimen (subsequently called slice), provided that appropriate test methods for oxygen content are selected.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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1.1 This guide covers sputtering targets used as thin film source material in fabricating semiconductor electronic devices. It should be used to develop target specifications for specific materials and should be referenced therein.
1.2 This standard sets purity grade levels, analytical methods and impurity content reporting method and format.
1.2.1 The grade designation is a measure of total metallic impurity content. The grade designation does not necessarily indicate suitability for a particular application because factors other than total metallic impurity may influence performance.
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1.1 This test method covers measurement of the resistivity profile perpendicular to the surface of a silicon wafer of known orientation and type.
Note 1--This test method may also be applicable to other semiconductor materials, but feasibility and precision have been evaluated only for silicon and germanium.
1.2 This test method may be used on epitaxial films, substrates, diffused layers, or ion-implanted layers, or any combination of these.
1.3 This test method is comparative in that the resistivity profile of an unknown specimen is determined by comparing its measured spreading resistance value with those of calibration standards of known resistivity. These calibration standards must have the same surface preparation, conductivity type, and crystallographic orientation as the unknown specimen.
1.4 This test method is intended for use on silicon wafers in any resistivity range for which there exist suitable standards. Polished, lapped, or ground surfaces may be used.
1.5 This test method is destructive in that the specimen must be beveled.
1.6 Correction factors, which take into account the effects of boundaries or local resistivity variations with depth, are needed prior to using calibration data to calculate resistivity from the spreading resistance values.
Note 2--This test method extends Method F525 to depth profiling.
Note 3--This test method provides means for directly determining the resistivity profile of a silicon specimen normal to the specimen surface. Unlike Test Methods F84, F374, F1392, and F1393, it can provide lateral spatial resolution of resistivity on the order of a few micrometres, and an in-depth spatial resolution on the order of 10 nm (100 A). This test method can be used to profile through p-n junctions.
1.7 This test method is primarily a measurement for determining the resistivity profile in a silicon wafer. However, common practice is to convert the resistivity profile information to a density profile. For such purposes, a conversion between resistivity and majority carrier density is provided in Appendix X2.
1.8 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use. Specific hazard statements are given in Section 9.
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1.1 This test method covers the quantitative determination of surface trace metal contamination on the surface of polycrystalline silicon using an acid to extract the metals from the surface. The metals content of the acid is then analyzed by graphite furnace atomic-absorption spectroscopy.
1.2 This test method can be used for various rod, chunk, granule and chip sizes, for polycrystalline or single crystal silicon, to determine surface metal contaminants. Since the area of irregularly-shaped chunks, chips, or granules is difficult to measure accurately, values are based on sample weight. Using a sample weight of 300 g allows detection limits at the 0.1 ppbw (parts per billion weight) level.
1.3 The strength, composition, temperature, and exposure time of the acid determine the depth of surface etching and the efficiency of the extraction of the contaminants from the surface. Less than 1 % of the sample weight is removed in this test method.
1.4 This test method is useful for determining the alkali elements, alkali earth, and first series transition elements, such as sodium, potassium, calcium, iron, chromium, nickel, copper, zinc, as well as other elements such as aluminum. The recovery of these elements from the silicon surface is measured as greater than 90 %, using control standards intentionally added to the polysilicon surface.
1.5 This test method suggests a particular sample size, acid composition, etch cycle, testing environment, and instrument protocol. Variations in these parameters may be used, but may effect the recovery efficiency or retention of metals during processing. In practice, this test method is used for sample weights of 25 to 5000 g. For referee purposes, this test method specifies a sample weight of 300 g. This test method includes guidelines to alert the analyst to the interferences and resultant variations in this test method, and includes standard methods for quantifying and reporting these variations.
1.6 This test method specifies the use of graphite furnace atomic-absorption spectroscopy to analyze trace metals content of the acid extract. Other instruments of equivalent sensitivity, such as inductively-coupled plasma/mass spectrometry, may be used.
1.7 The detection limit and method variation depend on the efficiency of the acid extraction procedure, sample size, the method interferences, the absorption spectrum of each element, and the instrumental sensitivity, background, and blank value.
1.8 This test method uses hot acid to etch away the surface of the silicon. The etchant is potentially harmful and must be handled in an acid exhaust fume hood, with utmost care at all times. Hydrofluoric acid solutions are particularly hazardous and should not be used by anyone who is not familiar with the specific preventive measures and first aid treatments given in the appropriate Material Safety Data Sheet.
1.9 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use. Specific precautionary statements are given in Section 9.
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1.1 This test method provides procedures for the determination of relative radial variation of resistivity of semiconductor wafers cut from silicon single crystals grown either by the Czochralski or floating-zone technique.
1.2 This test method provides procedures for using Test Method F84 for the four-point probe measurement of radial resistivity variation.
1.3 This test method yields a measure of the variation in resistivity between the center and selected outer regions of the specimen. The amount of information obtained regarding the magnitude and form of the variation in the intervening regions when using the four-point probe array depends on the sampling plan chosen (see 7.2). The interpretation of the variations measured as radial variations may be in error if azimuthal variations on the wafer or axial variations along the crystal length are not negligible.
1.4 This test method can be applied to single crystals of silicon in circular wafer form, the thickness of which is less than one-half of the average probe spacing, and the diameter of which is at least 15 mm (0.6 in.). Measurements can be made on any specimen for which reliable resistivity measurements can be obtained. The resistivity measurement procedure of Test Method F84 has been tested on specimens having resistivities between 0.0008 and 2000 cm for p-type silicon and between 0.0008 and 6000 cm for n-type silicon. Geometrical correction factors required for these measurements are included for the case of standard wafer diameters, and are available in tabulated form for other cases.
Note 1--In the case of wafers whose thickness is greater than the average spacing of the measurement probes, no geometrical correction factor is available except for measurement at the center of the wafer face.
1.5 Several sampling plans are given which specify sets of measurement sites on the wafers being tested. The sampling plans allow differing levels of detail of resistivity variation to be obtained. One of these sampling plans shall be selected and agreed upon by the parties to the measurement. The basic resistivity measurements of Test Method F 84 are then applied at each site specified in the chosen sampling plan.
1.6 Results are expressed as relative changes in resistivity between the several measurement sites. To obtain absolute values of resistivity it is necessary to measure and correct for specimen temperature (see 11.1.4).
1.7 The values stated in SI units are to be regarded as the standard. The values given in parentheses are for information only.
1.8 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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