SIST EN 300 462-5-1 V1.1.2:2003
(Main)Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 5-1: Timing characteristics of slave clocks suitable for operation in Synchronous Digital Hierarchy (SDH) equipment
General Information
- Abstract
Stadardises SDH timing distribution architectures, synchronisation network level jitter and wander requirements, slave clock timing specifications and primary reference clock specifications.
- Status
- Published
- Publication Date
- 30-Nov-2003
- Current Stage
- 6060 - National Implementation/Publication (Adopted Project)
- Start Date
- 01-Dec-2003
- Due Date
- 01-Dec-2003
- Completion Date
- 01-Dec-2003
Overview
SIST EN 300 462-5-1 V1.1.2:2003 defines the generic requirements for synchronization networks, with a focus on the timing characteristics of slave clocks (SDH Equipment Clocks, SECs) used in Synchronous Digital Hierarchy (SDH) equipment. Prepared by the Slovenian Institute for Standardization (SIST) and harmonized with the European EN 300 462-5-1 standard, this document provides foundational requirements for ensuring reliable SDH timing distribution, precise synchronization, and effective management of jitter and wander in digital transmission systems.
Synchronization is a critical element in telecommunications networks, enabling the accurate alignment of digital signals. Effective timing distribution in SDH equipment is essential for high network reliability and data integrity, making slave clock performance crucial for network operators, equipment manufacturers, and integrators.
Key Topics
- Synchronization Network Architecture: Defines levels and methods for distributing synchronization signals in SDH networks, ensuring interoperability and consistent timing across multiple network elements.
- Jitter and Wander Specifications: Establishes maximum allowable jitter and wander (two forms of timing instability) for slave clocks under different environmental and operational conditions, supporting performance compliance across interfaces and network configurations.
- Slave Clock (SEC) Performance: Details frequency accuracy, noise generation, pull-in/pull-out range, transfer characteristics, holdover performance, and short/long term transient response for SDH slave clocks.
- Noise Tolerance: Specifies the minimum phase noise that slave clocks must accommodate at synchronization input points without loss of performance, covering both input jitter and wander tolerance.
- Primary Reference Clock (PRC) Interaction: Aligns slave clock requirements with those of the primary reference clock to maintain end-to-end timing stability within SDH synchronization networks.
Applications
This standard is vital in the following contexts:
- SDH Network Equipment: Ensures new hardware such as multiplexers, switches, and routers can reliably synchronize using standardized slave clock performance.
- Network Modernization and Upgrades: Provides criteria for evaluating existing or prospective SDH equipment for compliance with contemporary synchronization requirements.
- Interoperability: Facilitates integration of multi-vendor SDH equipment by harmonizing timing characteristics, thus supporting seamless network expansion and risk reduction.
- Testing and Certification: Guides network operators and third-party laboratories in verifying clock timing, jitter, wander, and holdover performance during equipment certification.
- Network Planning: Enables network engineers to design synchronization architectures that comply with international best practices, reducing errors caused by timing discrepancies.
By adhering to SIST EN 300 462-5-1 V1.1.2:2003, organizations ensure that synchronization networks in SDH environments are robust against timing disturbances and compliant with global standards for timing accuracy, noise tolerance, and transient response.
Related Standards
- EN 300 462-1-1: Definitions and terminology for synchronization networks.
- EN 300 462-2-1: Synchronization network architecture.
- EN 300 462-4-1: Timing characteristics of slave clocks for SDH and PDH equipment.
- EN 300 462-6-1: Timing characteristics for Primary Reference Clocks (PRC).
- ITU-T G.825: Control of jitter and wander in SDH-based digital networks.
- ITU-T G.703: Physical/electrical characteristics of hierarchical digital interfaces.
- ETS 300 019: Environmental conditions and tests for telecom equipment.
- ETS 300 417-1-1: Functional requirements for SDH equipment.
Adopting SIST EN 300 462-5-1 V1.1.2:2003 ensures technical consistency and best practice in SDH synchronization, supporting future-proof telecommunications infrastructure.
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Frequently Asked Questions
SIST EN 300 462-5-1 V1.1.2:2003 is a standard published by the Slovenian Institute for Standardization (SIST). Its full title is "Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 5-1: Timing characteristics of slave clocks suitable for operation in Synchronous Digital Hierarchy (SDH) equipment". This standard covers: Stadardises SDH timing distribution architectures, synchronisation network level jitter and wander requirements, slave clock timing specifications and primary reference clock specifications.
Stadardises SDH timing distribution architectures, synchronisation network level jitter and wander requirements, slave clock timing specifications and primary reference clock specifications.
SIST EN 300 462-5-1 V1.1.2:2003 is classified under the following ICS (International Classification for Standards) categories: 33.040.20 - Transmission systems. The ICS classification helps identify the subject area and facilitates finding related standards.
SIST EN 300 462-5-1 V1.1.2:2003 is available in PDF format for immediate download after purchase. The document can be added to your cart and obtained through the secure checkout process. Digital delivery ensures instant access to the complete standard document.
Standards Content (Sample)
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 5-1: Timing characteristics of slave clocks suitable for operation in Synchronous Digital Hierarchy (SDH) equipment33.040.20Prenosni sistemTransmission systemsICS:Ta slovenski standard je istoveten z:EN 300 462-5-1 Version 1.1.2SIST EN 300 462-5-1 V1.1.2:2003en01-december-2003SIST EN 300 462-5-1 V1.1.2:2003SLOVENSKI
STANDARD
EN 300 462-5-1 V1.1.2 (1998-05)European Standard (Telecommunications series)Transmission and Multiplexing (TM);Generic requirements for synchronization networks;Part 5-1: Timing characteristics of slave clocks suitable foroperation in Synchronous Digital Hierarchy (SDH) equipmentSIST EN 300 462-5-1 V1.1.2:2003
ETSIEN 300 462-5-1 V1.1.2 (1998-05)2ReferenceREN/TM-03017-5-1 (4a199idc.PDF)Keywordssynchronization, timing, transmissionETSIPostal addressF-06921 Sophia Antipolis Cedex - FRANCEOffice address650 Route des Lucioles - Sophia AntipolisValbonne - FRANCETel.: +33 4 92 94 42 00
Fax: +33 4 93 65 47 16Siret N° 348 623 562 00017 - NAF 742 CAssociation à but non lucratif enregistrée à laSous-Préfecture de Grasse (06) N° 7803/88Internetsecretariat@etsi.frhttp://www.etsi.frhttp://www.etsi.orgCopyright NotificationNo part may be reproduced except as authorized by written permission.The copyright and the foregoing restriction extend to reproduction in all media.© European Telecommunications Standards Institute 1998.All rights reserved.SIST EN 300 462-5-1 V1.1.2:2003
ETSIEN 300 462-5-1 V1.1.2 (1998-05)3ContentsIntellectual Property Rights.5Foreword.51Scope.72References.73Definitions, symbols and abbreviations.83.1Definitions.83.2Abbreviations.84Frequency accuracy.85Pull-in and pull-out ranges.86Noise generation.86.1Wander in locked mode.96.2Non-locked wander.106.3Jitter.106.3.1Output jitter at a 2 048 kHz and 2 048 kbit/s interface.106.3.2Output jitter at a Synchronous Transport Module N (STM-N) interface.117Noise tolerance.117.1Jitter tolerance.117.2Wander tolerance.128Transfer characteristic.149Transient response and holdover performance.149.1Short-term phase transient response.149.2Long-term phase transient response (holdover).159.3Phase response to input signal interruptions.169.4Phase discontinuity.1610Interfaces.16Annex A (informative):Considerations on bandwidth requirements.18A.1Introduction.18A.2Relevant network requirements and assumptions.18A.2.1ITU-T Recommendation G.825 STM-N jitter acceptance.18A.2.2Wander accumulation in a synchronization distribution chain.18A.2.3Phase transients due to automatic timing restoration.19SIST EN 300 462-5-1 V1.1.2:2003
ETSIEN 300 462-5-1 V1.1.2 (1998-05)4A.3Conclusion.20Annex B (informative):Measurement methods for transfer characteristics.21B.1Phase step response.21B.2Frequency step response.22B.3Sinusoidal phase response.23B.4White phase noise response (frequency domain).23B.5White phase noise response (time domain).24Annex C (informative):Information on the SEC noise model.25Bibliography.26History.27SIST EN 300 462-5-1 V1.1.2:2003
ETSIEN 300 462-5-1 V1.1.2 (1998-05)5Intellectual Property RightsIPRs essential or potentially essential to the present document may have been declared to ETSI. The informationpertaining to these essential IPRs, if any, is publicly available for ETSI members and non-members, and can be foundin ETR 314: "Intellectual Property Rights (IPRs); Essential, or potentially Essential, IPRs notified to ETSI in respect ofETSI standards", which is available free of charge from the ETSI Secretariat. Latest updates are available on the ETSIWeb server (http://www.etsi.fr/ipr or http://www.etsi.org/ipr).Pursuant to the ETSI Interim IPR Policy, no investigation, including IPR searches, has been carried out by ETSI. Noguarantee can be given as to the existence of other IPRs not referenced in ETR 314 (or the updates on the ETSI Webserver) which are, or may be, or may become, essential to the present document.ForewordThis European Standard (Telecommunications series) has been produced by the Transmission and Multiplexing (TM)Technical Committee.The present document has been produced to provide requirements for synchronization networks that are compatible withthe performance requirements of digital networks. It is one of a family of documents covering various aspects ofsynchronization networks:Part 1-1:"Definitions and terminology for synchronization networks";Part 2-1:"Synchronization network architecture";Part 3-1:"The control of jitter and wander within synchronization networks";Part 4-1:"Timing characteristics of slave clocks suitable for synchronization supply to Synchronous DigitalHierarchy (SDH) and Plesiochronous Digital Hierarchy (PDH) equipment";Part 4-2:"Timing characteristics of slave clocks suitable for synchronization supply to Synchronous DigitalHierarchy (SDH) and Plesiochronous Digital Hierarchy (PDH) equipment ImplementationConformance (ICS) Statement";Part 5-1:"Timing characteristics of slave clocks suitable for operation in Synchronous DigitalHierarchy (SDH) equipment";Part 6-1:"Timing characteristics of primary reference clocks";Part 6-2:"Timing characteristics of primary reference clocks Implementation Conformance (ICS)Statement";Part 7-1:"Timing characteristics of slave clocks suitable for synchronization supply to equipment in localnode applications".Parts 1-1, 2-1, 3-1 and 5-1 have previously been published as ETS 300 462 Parts 1, 2, 3 and 5, respectively.Additionally, parts 4-1 and 6-1 completed the Voting phase of the Two Step Approval procedure as ETS 300 462 Parts4 and 6, respectively.It was decided to prepare ICS proformas for several of the parts and this necessitated a re-numbering of the individualdocument parts. It was also decided to create a new part 7-1.This in turn led to a need to re-publish new versions of all six parts of the original ETS. At the same time, theopportunity was taken to convert the document type to EN.This has involved no technical change to any of the documents. However part 5-1 has been modified, due to editorialerrors which appeared in ETS 300 462-5.SIST EN 300 462-5-1 V1.1.2:2003
ETSIEN 300 462-5-1 V1.1.2 (1998-05)6Transposition datesDate of adoption of this ETS:16 August 1996Date of latest announcement of this ETS (doa):31 December 1996Date of latest publication of new National Standardor endorsement of this ETS (dop/e):30 June 1997Date of withdrawal of any conflicting National Standard (dow):30 June 1997NOTE:The above transposition table is the original table from ETS 300 462-5 (September 1996, see History).SIST EN 300 462-5-1 V1.1.2:2003
ETSIEN 300 462-5-1 V1.1.2 (1998-05)71ScopeThis European Standard (Telecommunications series) outlines requirements for timing devices used in synchronisingnetwork equipment that operates according to the principles governed by the Synchronous Digital Hierarchy (SDH).These requirements apply under the normal environmental conditions specified for SDH equipment. Typical SDHequipment contains a slave clock linked to a master, or a primary reference clock. The logical function of the SEC isdescribed in figure 2 of EN 300 462-2-1 [3]. In general the SDH Equipment Clock (SEC) will have multiple referenceinputs. In the event that all links between the master and the slave clock fail, the equipment should be capable ofmaintaining operation (holdover) within the prescribed performance limits contained within the present document.Slave clocks used in SDH equipment shall meet specific requirements in order to comply with the jitter specificationsgiven in ETS 300 417-1-1 [9] for plesiochronous tributaries.The case where clock performance is required in SDH equipment is outside the scope of the present document, seeEN 300 462-4-1 [10].2ReferencesThe following documents contain provisions which, through reference in this text, constitute provisions of the presentdocument.· References are either specific (identified by date of publication, edition number, version number, etc.) ornon-specific.· For a specific reference, subsequent revisions do not apply.· For a non-specific reference, subsequent revisions do apply.· A non-specific reference to an ETS shall also be taken to refer to later versions published as an EN with the samenumber.[1]ETS 300 019: "Equipment Engineering (EE); Environmental conditions and environmental testsfor telecommunications equipment".[2]EN 300 462-1-1: "Transmission and Multiplexing (TM); Generic requirements for synchronizationnetworks; Part 1-1: Definitions and terminology for synchronization networks".[3]EN 300 462-2-1: "Transmission and Multiplexing (TM); Generic requirements for synchronizationnetworks; Part 2-1: Synchronisation network architecture".[4]ITU-T Recommendation G.823: "The control of jitter and wander within digital networks whichare based on the 2 048 kbit/s hierarchy".[5]EN 300 462-6-1: "Transmission and Multiplexing (TM); Generic requirements for synchronizationnetworks; Part 6-1: Timing characteristics of primary reference clocks".[6]ITU-T Recommendation G.703: "Physical/electrical characteristics of hierarchical digitalinterfaces".[7]ITU-T Recommendation G.825: "The control of jitter and wander within digital networks whichare based on the synchronous digital hierarchy (SDH)".[8]ITU-T Recommendation Q.551: "Transmission characteristics of digital exchanges".[9]ETS 300 417-1-1 (1996): "Transmission and Multiplexing (TM); Generic functional requirementsfor Synchronous Digital Hierarchy (SDH) equipment; Part 1-1: Generic processes andperformance".[10]EN 300 462-4-1: "Transmission and Multiplexing (TM); Generic requirements for synchronizationnetworks; Part 4-1: Timing characteristics of slave clocks suitable for synchronization supply toSynchronous Digital Hierarchy (SDH) and Plesiochronous Digital Hierarchy (PDH) equipment".SIST EN 300 462-5-1 V1.1.2:2003
ETSIEN 300 462-5-1 V1.1.2 (1998-05)83Definitions, symbols and abbreviations3.1DefinitionsFor the purposes of the present document, the definitions given in EN 300 462-1-1 [2] apply.3.2AbbreviationsFor the purposes of the present document, the abbreviations given in EN 300 462-1-1 [2], together with the following,apply:MTIEMaximum Time Interval ErrorNENetwork ElementPDHPlesiochronous Digital HierarchyPLLPhase Locked Loopppmparts per millionPRCPrimary Reference ClockSDHSynchronous Digital HierarchySECSDH Equipment ClockSSUSynchronisation Supply UnitSTM-NSynchronous Transport Module NTDEVTime DeviationUIUnit IntervalUIppUnit Interval peak to peakVCOVoltage Controlled Oscillator4Frequency accuracyUnder free-running conditions, the SEC output frequency accuracy shall be within 4,6 ppm with regard to a referencetraceable to a clock as specified in EN 300 462-6-1 [5].NOTE:The time interval for this accuracy specification is for further study.5Pull-in and pull-out rangesThe minimum pull-in range shall be ± 4,6 ppm, whatever the internal oscillator frequency offset may be. The Pull-outrange is for further study. A value of ± 4,6 ppm has been proposed.6Noise generationThe noise generation of a SEC represents the amount of phase noise produced at the output when there is an idealinput reference signal or the clock is in holdover state. A suitable reference, for practical testing purposes, implies aperformance level at least 10 times more stable than the output requirements. The ability of the clock to limit this noiseis described by its frequency stability. The measures Maximum Time Interval Error (MTIE) and Time Deviation(TDEV) are useful for characterization of noise generation performance.MTIE and TDEV are measured through an equivalent 10 Hz, first order, low-pass measurement filter, at a maximumsampling time t0 of 1/30 second. The minimum measurement period for TDEV is twelve times the integration period(T = 12t).SIST EN 300 462-5-1 V1.1.2:2003
ETSIEN 300 462-5-1 V1.1.2 (1998-05)96.1Wander in locked modeWhen the SEC is in the locked mode of operation, the MTIE and TDEV measured using the synchronised clockconfiguration defined in figure 1a of EN 300 462-1-1 [2] shall have the
limits in tables 1 and 2, if the temperature isconstant (± 1 K).Table 1: Wander in locked mode for constant temperature specified in MTIERequirementObservation interval40 ns0,1 < t £ 1 s40 t 0,1 ns1 < t £ 100 s25 t 0,2 ns100 < t £ 1 000 sTable 2: Wander in locked mode for constant temperature specified in TDEVRequirementObservation interval3,2 ns0,1 < t £ 25 s0,64 t 0,5 ns25 < t £ 100 s6,4 ns100 < t £ 1 000 sThe model used to derive these numbers is described in (informative) annex C. The resultant requirements are shown bythe thick solid lines in figures 1 and 2.101,0TDEV1025100(ns)(constant temperature)TDEVObservation Interval
(s)(log scale)(log scale)6,43,20,11,01 000tFigure 1: TDEV as a function of an observation period ttSIST EN 300 462-5-1 V1.1.2:2003
ETSIEN 300 462-5-1 V1.1.2 (1998-05)1010110001000.163401.0101001000113(ns)(constant temperature)MTIE(variable temperature)150Observation Interval(s)tMTIEMTIE(log scale)(log scale)Figure 2: MTIE as a function of an observation period tWhen temperature effects are included of which the limits and rate of change are defined in ETS 300 019 [1], theallowance for the total MTIE contribution of a single SEC increases by the
values in table 3.Table 3: Additional wander in locked mode for variable temperature specified in MTIERequirementObservation interval0,5 t nst £ 100 s50 nst > 100 sThe resultant requirement is shown by the upper solid line in figure 2.6.2Non-locked wanderWhen a clock is not locked to a synchronization reference, the random noise components are negligible compared todeterministic effects like initial frequency offset. Consequently the non-locked wander effects are included insubclause 9.1.6.3JitterWhile most specifications in the present document are independent of the output interface at which they are measured,this is not the case for jitter production; jitter generation specifications shall utilize existing specifications that arecurrently specified differently for different interface rates. These requirements are stated separately for the interfacesidentified in clause 10. To be consistent with other jitter requirements the specifications are in Unit Interval peak topeak (UIpp), where the Unit Interval (UI) corresponds to the reciprocal of the bit rate of the interface.Due to the stochastic nature of jitter, the peak-to-peak values given in this clause eventually are exceeded. Therequirements shall therefore be fulfilled with a probability of 99 %.6.3.1Output jitter at a 2 048 kHz and 2 048 kbit/s interfaceIn the absence of input jitter, the intrinsic jitter at a 2 048 kHz or 2 048 kbit/s output interface as measured over a 60seconds interval shall not exceed 0,05 UIpp when measured through a band-pass filter with corner frequencies at 20Hz and 100 kHz each with a first order 20 dB/decade roll-off characteristic.SIST EN 300 462-5-1 V1.1.2:2003
ETSIEN 300 462-5-1 V1.1.2 (1998-05)116.3.2Output jitter at a Synchronous Transport Module N (STM-N)interfaceIn the absence of input jitter at the synchronization interface, the intrinsic jitter at optical STM-N output interfaces asmeasured over a 60 seconds interval shall not exceed the limits given in table 4. The allowed jitter on an STM-1electrical interface is for further study.Table 4: Output jitter requirements for STM-N optical interfacesInterfaceMeasuring filter(Hz)Peak-to-peak amplitude(UI)STM-1500 to 1,3 M0,5065 k to 1,3 M0,10STM-41 k to 5 M0,50250 k to 5 M0,10STM-165 k to 20 M0,501 M to 20 M0,10for STM-1:1 UI = 6,43 ns;for STM-4:1 UI = 1,61 ns;for STM-16:1 UI = 0,40 ns.7Noise toleranceNoise tolerance of an SEC indicates the minimum phase noise level at the input of the clock that should beaccommodated whilst:-maintaining the clock within prescribed performance limits. The exact performance limits are for further study;-not causing any alarms;-not causing the clock to switch reference;-not causing the clock to go into holdover.In general, the noise tolerance is the same as the network limit for the synchronization interface in order to maintainacceptable performance. The jitter and wander tolerances given in subclauses 7.1 and 7.2 represent the worst levels thata synchronization carrying interface should exhibit. The requirements in subclause 7.1 have been derived by combiningthe most stringent requirements from each specific data interface and presenting them as a single specification whichdefines the performance of the SDH Equipment Clock (SEC). It is not expected that every synchronization interfaceshould tolerate the full requirements in figure 3. Consequently when testing a specific interface (e.g. an STM-N), theinterface is also bound by the jitter and wander tolerance limits defined in ITU-T Recommendations G.823 [4] andG.825 [7].7.1Jitter toleranceThe lower limits of maximum tolerable input jitter for signals carrying synchronization to SECs is given in figure 3 andtable 5.Table 5: Lower limit of maximum tolerable input jitterRequirementFrequency interval250 ns1 < f £ 19 Hz4 900 f -1 ns19 < f £ 49 Hz100 ns49 < f £ 105 HzSIST EN 300 462-5-1 V1.1.2:2003
ETSIEN 300 462-5-1 V1.1.2 (1998-05)12101001k100k10k1949100250(ns)Peak-to-peakJitter AmplitudeJitter Frequency f(Hz)1M(log scale)(log scale)1,0Figure 3: Lower limit of maximum tolerable input jitter7.2Wander toleranceThe clock shall tolerate (i.e. shall give no indication of improper operation) input wander as specified in figures 4 and5 (and tables 6 and 7 respectively). The templates in these figures are intended to represent the cumulative networkwander at the SEC input, i.e. for synchronization inputs the required wander tolerance should at least be equal to thenetwork limit.MTIE and TDEV are measured through an equivalent 10 Hz, first order, low-pass measurement filter, at a maximumsampling time t0 of 1/30 second. The minimum measurement period for TDEV is twelve times the integration period(T = 12t).Table 6: Input wander tolerance specified in TDEVRequirementObservation interval12 ns0,1 < t £ 7 s1,7t ns7 < t £ 100 s170 ns100 < t £ 1 000 s10112TDEVObservation Interval
(s)(ns)1101001k1001707(log scale)(l
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