SIST HD 576 S1:1997

SLOVENSKI STANDARD
01-avgust-1997
IEC 60822 VSB – Vzporedni podsistem vodila IEC 60821 VMEbus
IEC 60822 VSB - Parallel sub-system Bus of the IEC 60821 VMEbus
IEC 60822 VSB - Parallel-Unterbussystem für den IEC 60821 VME-Bus
CEI 60822 VSB - Bus parallèle de sous-système de bus CEI 60821 VME bus
Ta slovenski standard je istoveten z: HD 576 S1:1990
ICS:
35.160 Mikroprocesorski sistemi Microprocessor systems
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

NORME CEI
INTERNATIONALE IEC
INTERNATIONAL
Première édition
STANDARD
First edition
1988-12
CEI 822 VSB
Bus parallèle de sous-système
du bus CEI 821 VMEbus
IEC 822 VSB
Parallel Sub-system Bus of the
IEC 821 VMEbus
© IEC 1988 Droits de reproduction réservés — Copyright - all rights reserved
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822 © IE C
CONTENTS
Page
FOREWORD 15
PREFACE 15
CHAPTER 0: SCOPE
CHAPTER 1: INTRODUCTION TO THE IEC 822 VSB BUS STANDARD
Section
1.1 Standard objectives of the IEC 822 VSB parallel Subsystem
Bus of the IEC 821 VMEbus (Subsystem henceforth referred to
as VSB) 19
1.2 VSB system elements 19
1.2.1 Basic definitions 19
1.2.1.1 Physical structure definition 19
1.2.1.2 Functional structure definition 21
1.2.1.3 Types of VSB cycles 25
1.3 VSB standard diagrams 31
1.4 Standard terminology 31
1.4.1 Signal line states 33
1.4.2 Use of the asterisk (*) 35
1.5 Protocol specification 35
CHAPTER 2: VSB DATA TRANSFER BUS
2.1 Introduction 39
2.2 Data Transfer Bus lines 41
2:2.1 Adressing lines 41
2.2.1.1 ADOO-AD31 41
2.2.1.2 SPACEO-SPACE1 43
2.2.1.3 SIZEO-SIZE1 43
2.2.1.4
ASACKO*-ASACK1* 43
2.2.1.5 GAO-GA2 45
2.2.2 Data lines ADOO-AD31 45
2.2.3 Control lines 45
' 2.2.3.1 PAS* 45
2.2.3.2 AC 47
WR* 2.2.3.3 47
2.2.3.4 LOCK* 47
2.2.3.5 DS* 47
2.2.3.6 WAIT* 47
2.2.3.7 ACK* 49
2.2.3.8 ERR* 49
2.2.3.9 IRQ* 49
2.2.3.10 CACHE* 51
2.3 DTB modules - Basic description 51
2.3.1 MASTER 53
2.3.2 SLAVE 55
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CI
Page
Section
Capabilities of MASTERS and SLAVES 57
2.4
61 2.4.1 Addressing capabilities
63 2.4.1.1 Basic addressing capabilities
65 2.4.1.2 ADDRESS-ONLY capability
67 2.4.2 Data transfer capabilities
67 2.4.2.1 Basic data transfer capability of MASTERS
2.4.2.2 Basic data transfer capabilities of SLAVES
71 2.4.2.3 Dynamic bus sizing
2.4.2.4 SINGLE-TRANSFER capability
2.4.2.5 BLOCK-TRANSFER capability 75
2.4.2.6 INDIVISIBLE-ACCESS capability
Interrupt capability 2.4.3
2.4.3.1 Basic interrupt capabilities of MASTERS and SLAVES
2.4.3.2 INTERRUPT-ACKNOWLEDGE cycle capabilities
91 2.5 Interaction between MASTERS and SLAVES
Interaction between MASTERS and SLAVES during address
2.5.1
broadcast phase
2.5.1.1 Flow of the address broadcast phase
99 2.5.1.2 Signaling during the address broadcast phase
Interaction between MASTERS and SLAVES during the data
2.5.2
transfer
107 2.5.2.1 Flow of a write data transfer
2.5.2.2 Flow of a read data transfer
2.5.2.3 Signaling during the data transfer phase
2.5.3 Interaction between MASTERS and SLAVES during cycle
termination
2.5.3.1 Flow of the termination of a cycle
2.5.4 Interaction between the IHV MASTER and SLAVES during
the INTERRUPT-ACKNOWLEDGE cycles
129 2.5.4.1 Flow of an INTERRUPT-ACKNOWLEDGE cycle
2.5.4.2 Signaling during the INTERRUPT-ACKNOWLEDGE cycle
2.6 Data transfer bus timing specifications
CHAPTER 3: VSB DATA TRANSFER BUS ARBITRATION
3.1 Introduction 189
3.1.1 Types of Arbitration
3.2 Arbitration Bus lines
3.2.1 BREQ*
3.2.2 BUSY*
3.2.3 BGIN*/BGOUT*
3.3 Arbitration modules - Basic description
3.3.1 ARBITER
3.3.2 REQUESTER
3.4 Capabilities of the REQUESTER 199
3.4.1 Serial Arbitration
3.4.1 1 Interaction between the ARBITER and SER REQUESTERS 203
3.4.1.2 Signaling during Serial Arbitration 209

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IEC
Section Page
3.4.2 Parallel Arbitration capability 213
3.4.2.1 Flow of an ARBITRATION cycle 213
3.4.2.2 Signaling during the ARBITRATION cycle 219
Power-up sequence 221
3.4.3
3.4.3.1 Flow of the power-up sequence 221
3.4.3.2 Interaction between arbitration bus modules during power-up
3.5 Interaction between the MASTER, its associated REQUESTER
and/or its associated ARBITER 229
3.5.1 Acquisition of the DTB
3.5.2 Release of the DTB 229
3.5.3 Race conditions between MASTER requests and ARBITER grants 231
3.6 Arbitration bus timing specifications 231
CHAPTER 4: ELECTRICAL CHARACTERISTICS OF VSB BOARDS
4.1 Introduction 253
4.1.1 Terminology 253
4.2 Power distribution
4.2.1 D.C. voltage characteristics 257
4.2.2 Connector electrical ratings 257
4.3 Bus driving and receiving requirements 257
4.3.1 General 257
4.3.2 Driving and loading RULES for three-state lines
(AD00-AD31, DS*, PAS*, LOCK*, SIZEO-SIZE1, SPACEO-SPACE1, WR*) 261
4.3.3 Driving and loading RULES for open-collector lines
(AC, ACK*, AD24-AD31, ASACKO*-ASACKI BREQ*, BUSY*, CACHE*,
ERR*, IRQ*, WAIT*) 265
4.3.4 Driving and loading RULES for BGIN* and BGOUT* 269
4.3.5 Receiving RULES for the geographical addressing lines
(GAO-GA2) 271
4.3.6 Additional information 271
4.4 Signal lines interconnection - Summary 273
CHAPTER 5: VSB BACKPLANE SPECIFICATIONS
5.1 Introduction 277
5.2 Backplane physical characteristics 277
5.3 Power distribution 281
5.4 Backplane electrical characteristics 281
5.4.1 Characteristic impedance 281
5.4.2 Termination networks 289
5.5 Signal line interconnection 293
5.5.1 General 293
5.5.2 BGIN*/BGOUT* daisy-chain 295
5.5.3 Geographical addressing 295
5.5.4 Additional information 297
5.6 VSB pin assignment
APPENDIX A 301
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Figure Page
1-1 Functional modules and sub-buses defined by the VSB standard 23
1-2 Signal timing notation 37
2-1 Data Transfer Bus functional block diagram 39
2-2 Block diagram: MASTER 53
2-3 Block diagram: SLAVE 55
2-4 General flow of a VSB cycle 59
2-5 General flow of an ADDRESS-ONLY cycle 65
2-6 Organization of data 67
2-7 General flow of a SINGLE-TRANSFER cycle 73
2-8 General flow of a BLOCK-TRANSFER cycle 77
2-9 General flow of an INTERRUPT-ACKNOWLEDGE cycle 87
2-10 Flow of the address broadcast phase 97
2-11 Flow of a write data transfer 111
2-12 Flow of a read data transfer 115
2-13 Flow of the termination of the cycle 127
2-14 Flow of an INTERRUPT-ACKNOWLEDGE cycle 133
2-15 Active MASTER, active IHV MASTER
and active PAR REQUESTER,
LOCK*, WR*, SIZEO-SIZE1 and SPACEO-SPACE1 timing,
SINGLE-TRANSFER,
BLOCK-TRANSFER,
INTERRUPT-ACKNOWLEDGE and
ARBITRATION cycles 147
2-16 Active MASTER and SLAVES,
address broadcast timing,
ADDRESS-ONLY,
SINGLE-TRANSFER and
BLOCK-TRANSFER cycles 149
2-17 Active MASTER and SLAVES, cycle termination
ADDRESS-ONLY cycles 151
2-18 Active MASTER and SLAVES,
write data transfer timing,
SINGLE-TRANSFER and
BLOCK-TRANSFER cycles 153
2-19 Active MASTER and SLAVES,
read data transfer timing,
SINGLE-TRANSFER,
BLOCK-TRANSFER and
INTERRUPT-ACKNOWLEDGE cycles 157
2-20 IHV MASTER and INTV SLAVES, selection phase INTERRUPT-
ACKNOWLEDGE cycles 161
2-21 MASTERS and SLAVES intercycle timing 163
2-22 DTB control transfer timing 165
2-23 Skew between ASACKO* and ASACK1* 167
2-24 Skew between ACK* and ERR* 167
3-1 Arbitration bus functional block diagram 189
3-2 Block diagram: ARBITER 195
3-3 Block diagram: SER REQUESTER 197
3-4 Block diagram: PAR REQUESTER 199
3-5 Serial Arbitration flow diagram: two REQUESTERS 205
3-6 General flow of an ARBITRATION cycle 213
3-7 Flow of an ARBITRATION cycle 217
3-8 Flow of the power-up sequence 225
3-9 Active PAR REQUESTER, contending PAR REQUESTER and idle SLAVE
ARBITRATION cycle 237
3-10 Power-up timing 239
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Figure Page
4-1 VSB signal levels 259
5-1 VSB backplane dimensions 279
5-2 Cross-section of a backplane microstrip signal line 283
5-3 Z versus line width 285
5-4 Co versus line width 285
5-5 Standard bus termination 291
5-6 BGIN`/BGOUT* daisy-chain illustration 295
5-7 Geographical addressing lines resistor/capacitor circuit 295
Al Flow of the selection phase 303
A2 Selection phase control; a high level block diagram 305
A3 An example for the selection logic 307
Table
2-1 RULES and PERMISSIONS that specify the use of the dotted lines
by the various types of MASTERS 53
2-2 RULES and PERMISSIONS that specify the use of the dotted lines
by the various types of SLAVES 55
2-3 Mnemonics that specify addressing capabilities 63
2-4 Mnemonic that specifies ADDRESS-ONLY capability 65
2-5 Mnemonics that specify the basic data transfer capabilities
of SLAVES 69
2-6 Mnemonic that specifies BLOCK-TRANSFER capability 79
2-7 Mnemonics that specify interrupt capabilities 85
2-8 Mnemonics that specify STATUS/ID transfer capabilities
of IHV MASTERS and INTV SLAVES 91
2-9 Use of SPACED and SPACE1 to select the address space 99
2-10 Encoding of SIZED and SIZE1 for requested size of the transfer 101
2-11 Use of AD00 and ADO1 to select the lowest addressed byte
location to be accessed
2-12 Encoding of SIZEO, SIZE1, ADOO and ADO1 to define the byte
locations to be accessed 103
2-13 Encoding of ASACKO* and ASACK1* to define the size of the SLAVE 105
2-14 Placement of valid data on AD00-AD31 by the active MASTER
during write cycles 117
2-15 Use of ADOO-AD31 by a D32 SLAVE to access byte locations 119
2-16 Use of AD16-AD31 by a D16 SLAVE to access byte locations 121
2-17 Use of AD24-AD31 by a D08 SLAVE to access byte locations 121
2-18 Use of SPACED, SPACE1 and WR* to select an INTERRUPT-ACKNOWLEDGE
cycle 137
2-19 Use of the data lines by D08, D16 and D32 INTV SLAVES
during INTERRUPT-ACKNOWLEDGE cycles 139
2-20 Active MASTER, responding SLAVE, participating SLAVE and idle
SLAVE timing parameters 143
2-21 IHV MASTER, responding INTV SLAVE, contending INTV SLAVE and
idle SLAVE timing parameters 145
2-22 MASTER, timing specifications 169
2-23 SLAVE, timing specifications 179

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822 © IEC
Page
Table
RULES and PERMISSIONS that specify the use of the dotted lines
3-1
by the various types of SER REQUESTERS
Mnemonics that are used to describe REQUESTERS 3-2
Use of SPACEO-SPACE1 and WR* to select an ARBITRATION cycle
3-3
Active PAR REQUESTER, contending PAR REQUESTER and idle SLAVE
3-4
timing parameters
3-5 Power-up timing parameters
Active REQUESTER timing specifications 3-6
245 Contending REQUESTER timing specifications
3-7
249 3-8 Power-up timing specifications
Bus driving and receiving requirements
4-1
4-2 Signal line interconnection - Summary
281 5-1 Bus voltage specification
293 5-2 Signal line termination
Geographical addressing slot assignment 297
5-3
5-4 VSB pin assignment
822 © IEC -
15 -
INTERNATIONAL ELECTROTECHNICAL COMMISSION
IEC 822 VSB
PARALLEL SUB - SYSTEM BUS
OF THE IEC 821 VMEbus
FOREWORD
1) The formal decisions or agreements of the IEC on technical matters,
prepared by Technical Committees on which all the National Committees
having a special interest therein are represented, express, as nearly
as possible, an international consensus of opinion on the subjects
dealt with.
2) They have the form of recommendations for international use and they
are accepted by the National Committees in that sense.
3) In order to promote international unification, the IEC expresses the
wish that all National Committees should adopt the text of the IEC
recommendation for their national rules in so far as national
conditions will permit. Any divergence between the IEC recommendation
and the corresponding national rules should, as far as possible, be
clearly indicated in the latter.
4) The IEC has not laid down any procedure concerning marking as an
indication of approval and has no responsibility when an item of
equipment is declared to comply with one of its recommendations.
PREFACE
This standard has been prepared by Sub-Committee 47B: Microprocessor
Systems, of IEC Technical Committee No. 47: Semiconductor Devices.
The text of this standard is based on the following documents:
Six Months' Rule Report on Voting
47B(CO)22 478(C0)27
Further information can be found in the Report on Voting indicated in
the table above.
The following IEC publications are quoted in this standard:
Publications Nos. 603-2 (1980): Connectors for frequencies below 3 MHz
for use with printed boards, Part 2:
Two-part connectors for printed boards,
for basic grid of 2.54 mm (0.1 in) with
common mounting features.
821 (1987): IEC 821 BUS - Microprocessor system bus
for 1 to 4 byte data.
822 © IEC - 17 -
IEC 822 VSB
PARALLEL SUB - SYSTEM BUS
OF THE IEC 821 VMEbus
CHAPTER 0: SCOPE
The introduction of high performance of 32-bit microprocessors, as
well as the demands placed on microcomputers by the user community
have created a need for multiprocessor systems built from board level
products. The increase in the number of functions that such systems
provided necessitated the introduction of a
...