SIST HD 593.1 S1:1997

SLOVENSKI STANDARD
01-avgust-1997
0LNURSURFHVRUVNLVLVWHP%86]DLQELWQHSRGDWNH08/7,%86,GHO
)XQNFLRQDOQLRSLV]HOHNWULþQLPLLQþDVRYQLPLVSHFLILNDFLMDPL,(&
Microprocessor system BUS - 8-bit and 16-bit data (MULTIBUS I) -- Part 1: Functional
description with electrical and timing specifications
Mikroprozessor-Systembus I für 8 Bit- und 16 Bit-Datenübertragung (MULTIBUS I) -- Teil
1: Funktionsbeschreibung, elektrische Anforderungen und Zeitverhalten
BUS système à microprocesseurs - Données: 8 bits et 16 bits (MULTIBUS 1) -- Partie 1:
Description fonctionnelle avec spécifications électriques et chronologiques
Ta slovenski standard je istoveten z: HD 593.1 S1:1992
ICS:
35.160 Mikroprocesorski sistemi Microprocessor systems
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

NORME
CEI
INTERNATIONALE IEC
60796-1
INTERNATIONAL
Première édition
STAN DARD
First edition
1990-09
Bus système à microprocesseurs –
Données: 8 bits et 16 bits (MULTIBUS I)
Première partie:
Description fonctionnelle avec spécifications
électriques et chronologiques
Microprocessor system bus –
8-bit and 16-bit data (MULTIBUS I)
Part 1:
Functional description with electrical
and timing specifications
IEC 1990 Droits de reproduction réservés
© — Copyright - all rights reserved
Aucune partie de cette publication ne peut être reproduite ni No part of this publication may be reproduced or utilized in
utilisée sous quelque forme que ce soit et par aucun any form or by any means, electronic or mechanical,
procédé, électronique ou mécanique, compris la photo- including photocopying and microfilm, without permission in
y
copie et les microfilms, sans l'accord écrit de l'éditeur: writing from the publisher.
International Electrotechnical Commission 3, rue de Varembé Geneva, Switzerland
Telefax: +41 22 919 0300 e-mail: inmail@iec.ch IEC web site http: //www.iec.ch
CODE PRIX v /^
Commission Electrotechnique Internationale
PRICE CODE /^/`^
International Electrotechnical Commission
IEC MeiHpyHapogHaa 3nenrporexHwiecKaa HonnHCCHR
Pour prix, voir catalogue en vigueur
• • For price, see current catalogue

796-1 © IEC - 3 -
CONTENTS
Page
FOREWORD 9
PREFACE 13
INTRODUCTION 13
SECTION ONE - GENERAL
Clause
1.1 Scope 13
1.2 Object 15
1.3 Definitions 15
1.3.1
General System Terms 15
1.3.1.1
Compatibility (IEC Publication 625-1) 15
1.3.1.2
Bus Cycle 17
1.3.1.3
Interface (IEC Publication 625-1) 17
1.3.1.4 Interface System (IEC Publication 625-1) 17
1.3.1.5 Override 17
1.3.1.6 System 17
1.3.2 Signals and Paths (IEC Publication 625-1) 17
1.3.2.1
Bus (IEC Publication 625-1) 17
1.3.2.2
Byte 17
1.3.2.3 Word 17
1.3.2.4
Signal (IEC Publication 625-1) 17
1.3.2.5
Signal Parameter (IEC Publication 625-1) 19
1.3.2.6
Signal Level (IEC Publication 625-1) 19
1.3.2.7 High State (IEC Publication 625-1) 19
1.3.2.8
Low State (IEC Publication 625-1) 19
1.3.2.9
Signal Line (IEC Publication 625-1) 19
1.3.2.10 Master 19
1.3.2.11 Slave 19
SECTION TWO - FUNCTIONAL SPECIFICATIONS
2.1 Bus Elements 21
2.1.1 Masters 21
2.1.2 Slaves 23
2.1.3 Bus Signals 23
2.1.3.1
Control Lines 25
2.1.3.1.1
Clock Lines 25
2.1.3.1.2
Command Lines (MWTC*, MRDC*, IOWC*, IORC*) 25
2.1.3.1.3
Transfer Acknowledge Line (XACK*) 27
2.1.3.1.4
Initialize (INIT*) 27
2.1.3.1.5
Lock (LOCK*) 27
2.1.3.2 Address and Inhibit Lines 27

796-1 © IEC 5
Clause Page
2.1.3.2.1 Address Lines (24 lines) 27
2.1.3.2.2 Byte High Enable Line (BHEN*) 27
2.1.3.2.3 Inhibit Lines (INH1* and INH2*) 29
2.1.3.3 Data Lines (D0*-D15*)
2.1.3.4 Interrupt Lines
2.1.3.4.1 Interrupt Request Lines (INTO*-INT7*) 29
2.1.3.4.2 - Interrupt Acknowledge (INTA*) 29
2.1.3.5 Bus Exchange Lines 31
2.1.3.5.1 Bus Request (BREQ*) 31
2.1.3.5.2 Bus Priority (BPRN* and BPRO*) 31
2.1.3.5.3 Bus Busy (BUSY*)
2.1.3.5.4 Common Bus Request (CBRQ*) 31
2.2 Data Transfer Operation 31
2.2.1 Data Transfer Overview
2.2.2 Signal Descriptions 35
2.2.2.1 Initialize (INIT*) 35
2.2.2.2 Constant Clock (CCLK*) 37
2.2.2.3 Address Lines (A0*-A23*) 37
2.2.2.4 Data Lines (D0*-D15*) 37
2.2.2.5 Bus Commands
2.2.2.5.1 Read Operation
2.2.2.5.2 Write Operation 45
2.2.2.5.3 Transfer Acknowledge (XACK*)
2.2.2.5.4 Inhibit (INH1* and INH2*)
2.2.2.6 Lock (LOCK*)
2.3 Interrupt Operations
2.3.1 Interrupt Signal Lines 53
Interrupt Request Lines (INTO*-INT7*) 53
2.3.1.1
2.3.1.2 Interrupt Acknowledge (INTA*) 55
2.3.2 Classes of Interrupt Implementation 55
Non-Bus Vectored Interrupts 55
2.3.2.1
2.3.2.2 Bus Vectored Interrupts 57
2.4 Bus Exchange 59
2.4.1 Bus Exchange Signals 59
2.4.1.1 Bus Clock (BCLK*) 59
2.4.1.2 Bus Busy (BUSY*) 61
Bus Priority IN (BPRN*) 61
2.4.1.3
Bus Priority OUT (BPRO*) 63
2.4.1.4
2.4.1.5 Bus Request (BREQ*) 63
2.4.1.6 Common Bus Request (CBRQ*) (Optional) 63
Bus Exchange Priority Techniques 65
2.4.2
2.4.2.1 Serial Priority Technique
2.4.2.2 Parallel Arbitration Technique
SECTION THREE - ELECTRICAL SPECIFICATIONS
3.1 General Bus Considerations
3.1.1 Logical and Electrical State Relationships
3.1.2 Signal Line Characteristics 71
3.1.2.1 In-Use Signal Line Requirements
3.1.2.2 Backplane Signal Trace Characteristics

796-1 © IEC - 7
Clause Page
3.1.3 Power Supply Specification 73
3.1.4 Temperature and Humidity 79
3.2 Timing 79
3.2.1 Read Operations (I/O and Memory) 85
3.2.2 Write Operations (I/O and Memory) 85
3.2.3 Inhibit Operations 87
3.2.4 Interrupt Implementations 87
3.2.4.1 NBV Interrupts 89
3.2.4.2 BV Interrupts 89
3.2.5 Bus Control Exchanges 91
3.2.5.1 Serial Priority 93
3.2.5.2 Parallel Priority 95
3.2.6 Miscellaneous Timing 95
3.3 Receivers, Drivers and Terminations 97
SECTION FOUR - LEVELS OF COMPLIANCE
4.1 Variable Elements of Capability 105
4.1.1 Data Path 105
4.1.2 Memory Address Path 105
4.1.3 I/O Address Path 105
4.1.4 Interrupt Attributes 105
4.2 Masters and Slaves 107
4.3 Compliance Level Notation 109
4.3.1 Data Path 109
4.3.2 Memory Address Path 109
4.3.3 I/O Address Path 109
4.3.4 Interrupt Attributes 109
4.3.5 Example 109
4.3.6 Compliance Marking 111

796-1 © IEC - 9 -
INTERNATIONAL ELECTROTECHNICAL COMMISSION
MICROPROCESSOR SYSTEM BUS - 8-BIT AND 16-BIT DATA
(MULTIBUS I)
Part 1: Functional description with electrical
and timing specifications
FOREWORD
1) The formal decisions or agreements of the IEC on technical matters,
prepared by Technical Committees on which all the National Committees
having a special interest therein are represented, express, as nearly
as possible, an international consensus of opinion on the subjects
dealt with.
2) They have the form of recommendations for international use and they
are accepted by the National Committees in that sense.
In order to promote international unification, the IEC expresses the
3)
wish that all National Committees should adopt the text of the IEC
recommendation for their national rules in so far as national con-
ditions will permit. Any divergence between the IEC recommendation and
the corresponding national rules should, as far as possible, be clearly
indicated in the latter.
The IEC has not laid down any procedure concerning marking as an
4)
indication of approval and has no responsibility when an item of
equipment is declared to comply with one of its recommendations.
PREFACE
This standard has been prepared by Sub-Committee 47B*: Microprocessor
Systems, of IEC Technical Committee No. 47: Semiconductor Devices.
This standard forms Part 1 of a series of publications, the other parts
being:
- Publication 796-2 (1990): Microprocessor system bus - 8-bit and
16-bit data (MULTIBUS I) - Part 2: Mech-
anical and pin descriptions for the system
bus configuration, with edge connectors
(direct).
- Publication 796-3 (1990) : Part 3: Mechanical and pin descriptions for
the Eurocard configuration with pin and
socket (indirect) connectors.
796-1 © IEC
The text of this standard is based upon the following documents:
Six Months' Rule Report on Voting
47B(C0)8
47B(C0)14
Full information on the voting for the approval of this standard can be
found in the Voting Report indicated in the above table.
The following IEC publication is quoted in this standard:
Publication No. 625-1 (1979): An interface system for programmable
measuring instruments (byte serial, bit
parallel), Part 1: Functional specifica-
tions, electrical specifications, mechan-
ical specifications, system applications
and requirements for the designer and
user.
IEC Sub-Committee 47B has now been transferred to ISO/IEC JTC 1.
This standard was approved according to IEC procedures and is therefore
published as an IEC standard.
796-1 © IEC - 13 -
MICROPROCESSOR SYSTEM BUS - 8-BIT AND 16-BIT DATA
(MULTIBUS I)
Part 1: Functional description with electrical
and timing specifications
INTRODUCTION
This standard is one of a series which deals with the electrical and
mechanical interfaces to allow various microprocessor system components to
interact with each other. The interface bus serves as a parallel transfer
and utility signal interconnect for closely coupled system components. The
series consists of one functional description and two alternative mechanical
standards.
SECTION ONE - GENERAL
1.1 Scope
This standard is applicable to interface system components, for use
in interconnecting data processing, data storage, and peripheral
control devices in a closely coupled configuration. This interface
system contains the necessary signals to allow the various system
components to interact with each other. It allows memory and Input/
Output (I/O) data transfers, direct memory accesses, generation of
interrupts, etc. This standard provides a detailed description of all
the elements and features that make up the system bus.
The bus supports two independent address spaces: memory and I/O.
During memory cycles the bus allows direct addressability of up to 16
megabytes using 24-bit addressing. During I/O bus cycles, the bus
allows addressing of up to 64K I/O ports using 16-bit addressing.
Both memory and I/O cycles can support 8-bit data transfers.
The bus structure is built upon the master-slave concept where the
master device in the system takes control of the bus and the slave
device, upon decoding its address, acts upon the command provided
by the master. This handshake (master-slave relationship) between the
master and slave devices allows modules of different speeds to be
interfaced via the bus. It also allows data rates up to five million
transfers per second (bytes or words) to take place across the bus.
Another important feature of the bus is the ability to connect
multiple master modules for multiprocessing configurations. The bus
provides control signals for connecting multiple masters in either a
serial or parallel priority fashion. With either of these two arrange-
ments, more than one master may share bus resources.

796-1 @ IEC - 15 -
This standard has been prepared for those . users who intend to
evaluate or design products that will be compatible with the system
bus structure. To this end, the necessary signal definitions and timing
and electrical specifications have been covered in detail.
This standard deals only with the interface characteristics of
microcomputer devices and not with design specifications, performance
requirements, and safety requirements of modules.
Throughout this standard, the term "system" denotes the byte or
word interface system that, in general, includes all the circuits,
connectors, and control protocol to effect unambiguous data transfer
between devices. The term "device" or "module" denotes any product
connected to the interface system that communicates information via the
bus, and that conforms to the interface system definition.
1.2 Object
This standard is intended to:
1)
define a general purpose microcomputer system bus;
2) specify the device-independent electrical and functional interface
requirements that a module shall meet in order to interconnect and
communicate unambiguously via the bus system;
3) specify the terminology and definitions related to the system;
4) enable the interconnection of independently manufactured devices
into a single functional system;
5) permit products with a wide range of capabilities to be inter-
connected to the system simultaneously;
6) define a system with a minimum of restrictions on the performance
characteristics of devices connected to the system.
1.3
Definitions
The following general definitions apply for the purpose of this
standard. More detailed definitions can be found in the relevant
sub-clause.
1.3.1 General System Terms
1 .3.1 .1
Compatibility (IEC Publication 625-1)
The degree to which devices may be interconnected and used, with-
out modification, when designed as defined throughout this
standard
(e.g. mechanical, electrical, functional).

796-1 © IEC - 17 -
1.3.1.2 Bus Cycle
The process whereby digital signals effect the transfer of data bytes
or words across the interface by means of an interlocked sequence of
control signals. ".Interlocked" denotes a fixed sequence of events in
which one event shall occur before the next event can occur.
1.3.1.3 Interface (IEC Publication 625-1)
A common boundary between a considered system and another
system, or between parts of a system, through which information is
conveyed.
1.3.1.4 Interface System (IEC Publication
625-1)
The set of device-independent mechanical, electrical and functional
elements of an interface necessary to effect communication among a set
of devices. Cables, connectors, driver and receiver circuits, signal
line descriptions, timing and control conventions and functional logic
circ
...