SIST-TP CEN/CLC/TR 18202:2025

SLOVENSKI STANDARD
01-november-2025
Slojni model kvantnega računalništva
Layer model of Quantum Computing
Schichtenmodell des Quantencomputings
Modèle en couches de l'informatique quantique
Ta slovenski standard je istoveten z: CEN/CLC/TR 18202:2025
ICS:
35.020 Informacijska tehnika in Information technology (IT) in
tehnologija na splošno general
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

TECHNICAL REPORT CEN/CLC/TR 18202

RAPPORT TECHNIQUE
TECHNISCHER REPORT
September 2025
ICS 35.020
English version
Layer model of Quantum Computing
Modèle en couches de l'informatique quantique Schichtenmodell des Quantencomputings

This Technical Report was approved by CEN on 11 August 2025. It has been drawn up by the Technical Committee CEN/CLC/JTC
22.
CEN and CENELEC members are the national standards bodies and national electrotechnical committees of Austria, Belgium,
Bulgaria, Croatia, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy,
Latvia, Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Republic of North Macedonia, Romania, Serbia,
Slovakia, Slovenia, Spain, Sweden, Switzerland, Türkiye and United Kingdom.

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Ref. No. CEN/CLC/TR 18202:2025 E
reserved worldwide for CEN national Members and for
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Contents Page
European foreword . 3
Introduction . 4
1 Scope . 5
2 Normative references . 5
3 Terms and definitions . 5
4 Abbreviations . 6
5 Overview . 6
6 Low level hardware and control layers . 8
6.1 Cryogenic solid state . 8
6.1.1 General. 8
6.1.2 Layer 1 – Quantum devices . 8
6.1.3 Layer 2 – Control highway . 8
6.1.4 Layer 3 – Control electronics . 9
6.1.5 Layer 4 – Control software . 9
6.2 Room temperature solid state . 10
6.3 Trapped ions . 10
6.4 Neutral atoms . 11
6.5 Photonic quantum computing . 11
6.6 Other architectures . 11
7 Hardware abstraction layer (HAL) . 12
7.1 General. 12
7.2 Organization of qubits . 12
7.3 The concept of native gates . 12
7.4 Concept of primitive gates . 14
7.5 Concept of measurement . 15
7.6 Interfacing considerations . 15
8 Assembly layer . 15
9 Programming layer . 15
9.1 General. 15
9.2 Programming languages and libraries . 15
9.3 Quantum compilation. 16
10 Service layer . 16
11 Communication unit . 17
11.1 General. 17
11.2 Example information flow . 17
11.2.1 Single user accessing the full quantum stack . 17
11.2.2 Multiple users accessing the full quantum stack . 18
11.2.3 User accessing lower layer . 18
Bibliography . 19

European foreword
This document (CEN/CLC/TR 18202:2025) has been prepared by Technical Committee CEN/CLC/JTC 22
“Quantum Technologies”, the secretariat of which is held by DIN.
Attention is drawn to the possibility that some of the elements of this document may be the subject of
patent rights. CEN shall not be held responsible for identifying any or all such patent rights.
Any feedback and questions on this document should be directed to the users’ national standards body.
A complete listing of these bodies can be found on the CEN website.
Introduction
A layer model is an abstract description of a (computing) system via a common stack of layers. The model
for gate-based quantum computing, in scope of this Technical Report, slices down the overall complexity
of quantum computing into two main groups of layers, addressing this quantum system. The group of
lower layers addresses mainly hardware, and is dependent of the physical platform. The group of upper
layers addresses mostly software at a higher level of abstraction.
The group of lower (hardware) layers comprises multiple stacks, one for each identified architecture
family.
The higher up in the stack the more hardware-agnostic the inner layers of the upper (software) main
layer model will gradually be. By agnostic it is meant that the same system works for different quantum
computing hardware platforms such as solid state quantum computing, ion traps, neutral atoms, optical
quantum computing and topological quantum computing.
This structure decouples the software design from the hardware design to some extent, which has clear
advantages, such as the reputability of algorithms for different hardware. At the same time the structure
does not impose a fully hardware-agnostic group of upper layers to encompass the design of quantum
hardware and software in a co-design approach, that is, adapt software to make optimal use of the
hardware used and the vice versa. This approach is inevitable for current and near-future quantum
computer development, just as it turned out to be vital for classical computers in early stage and current
classical computing disciplines, e.g. in micro-controller design.
One purpose of this document is to define a common language that can be used to describe the features
and functional requirements for each layer of the stack of a quantum computer. Another purpose is to
analyse and describe the interaction between the layers by means of well-defined interfaces. These are
essential steps towards interworking between modules from different origins. The functional description
of each layer ought to offer sufficient guidance on where a desired functionality is to be described, and
what kind of exchange is needed with other modules through the interfaces. The boundaries between the
layers are natural locations for such interfaces. Correctly defining such boundaries demand for careful
analysis of the interaction between the layers.

This limitation keeps technologies like the universal adiabatic quantum-computing model, the universal photonic
one-way quantum computing model and its heuristic form quantum annealing, as out of scope if they do not
correspond to a gate-based quantum circuit.
1 Scope
This document defines a layer model that covers the entire stack of universal gate-based quantum
computers. The group of lower-level (hardware) layers are organized in different hardware stacks
tailored to different hardware architectures, while the group of higher-level (software) layers are built
on top of these and expected to be common for all quantum computing systems. The higher-up in the
stack, the more agnostic it will be from underlying layers. Reducing the dependencies between higher
and lower layers is a crucial point for optimized quantum computations. A co-requisite point is to allow
for a free but well-defined flow of information up and down the higher and lower layers to allow for co-
designing hardware and software.
The scope of this Technical Report is restricted to a universal gate-based quantum-computing model, also
known as a digital or circuit quantum-computing model, on multiple physical systems such as transmon,
spin-qubit, ion-trap, neutral-atom, and others. This document does not apply to technologies like the
universal adiabatic quantum-computing model and its heuristic form quantum annealing, if they do not
correspond to a gate-based quantum circuit. Due to major architecture differences in lower layers, it does
not apply either to the universal photonic one-way quantum computing model even though it is fully
compatible with gate-based quantum-computing model. Moreover, quantum computing models that are
not universal, such as quantum simulators and special purposes, are also out of scope.
Limiting the scope to a universal gate-based quantum computing model is justified by expected
commonalities at the higher layers, mainly above the hardware abstraction layer (HAL), up to the service
layer. These commonalities imply a market for software products usable for this wide range of quantum
computing technologies.
The present Technical Report is focussed on a high-level (functional) description of the layers involved.
Additional details of the individual layers are reserved for other future CEN/CLC/TRs.
2 Normative references
There are no normative references in this document.
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminology databases for use in standardization at the following addresses:
— ISO Online browsing platform: available at https://www.iso.org/obp/
— IEC Electropedia: available at https://www.electropedia.org/
3.1
codesign
design approach where (software) modules query lower layers for identifying the (hardware)
capabilities and limitations of a system and subsequently tailor their behaviour to these capabilities and
limitation
Note 1 to entry: This approach allows for hardware-specific optimizations and adaptations to optimize quantum
computations.
3.2
gate-based quantum computing
sequence of instructions (called a quantum circuit) to change the state of a quantum register with many
qubits before the resulting state is queried by measurements
Note 1 to entry: The instructions may comprise gates, mid-circuit measurements and state preparations. Gates are
unitary operations acting on a set of qubits. A gate-based quantum computer can be characterized by a gate set,
wherein the gate set is composed of gates which can be performed by the quantum computer.
3.3
Instruction Set Architecture
ISA
lower-level method of defining operations on a quantum computer
Note 1 to entry: Instead of defining specific gates, this method defines gates (or other instructions) as operations,
using pulses pulsed for a certain time, on specific qubits.
3.4
universal gate-based quantum computing
quantum computer capable of processing an arbitrary quantum circuit
Note 1 to entry: A universal gate-based quantum computer ought to have a gate set which is universal. A gate set is
said to be universal if any unitary operation may be approximated to arbitrary accuracy by a quantum circuit
involving only those gates [2]. The definition also comprises non-fault-tolerant universal quantum computers,
which can process an arbitrary quantum circuit reliably only up to a certain length, size or gate count.
4 Abbreviations
API Application Programming Interface
SDK Software Development Kit
ISA Instruction Set Architecture
PCB Printed Circuit Board
QEC Quantum Error Correction
HAL Hardware Abstraction Layer
RF Radio Frequency
DC Direct Current
AWG Arbitrary Waveform Generator
NV centre Nitrogen-Vacancy centre
5 Overview
Quantum computing is an area covering many different implementations. A convenient way of specifying
its requirements is via a stack of layers, as shown in Figure 1. The layers are chosen in such a manner that
the functionality of each layer can be described in an independent manner. This causes that the
interworking between these layers can be described through well-defined interfaces at the boundaries
of these layers. Note that such an interface can be virtual (hidden internally within the implementation
of the same origin) or real (between implementations of different origin).
The stack covers hardware and software layers, each having dedicated functionalities. A communication
unit connects the stack with the outside world to prevent unauthorized access to the stack. They are
described in succeeding chapters. The legend describing each colour can be seen in Figure 1. Each layer
aims to be more agnostic to the exact implementation of lower layers.
A module is within the context of this TR something that can be sold and shipped independently from
other modules. It can offer the functionality of a single layer, of multiple layers or just a fragment of a
layer. In all cases, they require interfaces to let them interwork with other modules. The boundaries
between the layers are natural locations for defining standardized interfaces between layers, so modules
can take advantage of that. But when the functionality of a module span two or more layers, there is no
need to implement the interfaces between the inner layers.
A module may also support different operating modes, such that it complies with different requirements
of multiple members and/or multiple architecture families.

Figure 1 — Overview of the layer model of quantum computing
Figure 1 shows an overview of the proposed layer model. In principle, each layer interacts only with the
one below and above it, but it is not excluded that interaction bypasses a layer to interact directly with
one deeper or higher. The communication unit can exchange information directly with each layer. The
dashed line separates the group of higher layers from the group of lower layers.
A one-size fits all approach may not apply to all these different architectures, and therefore each one may
have its own stack. The use of four lower layers have shown to be adequate for serving the needs of
cryogenic solid-state based technologies. Other architectures, depicted in this figure as technology #2
and #3, may need another composition of lower layers. Therefore their stack has been drawn as a single
box, and their details are left for further study.
It is possible that the layer above the dashed line accounts for different interfaces below the line that are
dedicated for each hardware stack. The aim of the hardware abstraction layer is to offer a more
harmonized and common interface to higher software layers.
So far, the following quantum architecture families have been identified (in arbitrary order):
— cryogenic solid-state based;
— room temperature solid-state based;
— trapped ions;
— neutral atoms;
— photonic quantum computing;
— molecular spins;
— other architectures that may be identified in the future.
These architectures are described in further detail in succeeding chapters.
Within an architecture family, multiple members may exist, like transmons and spin-qubits for cryogenic
solid state QC. Small differences in functionalities of the lower layers may therefore occur as well.
6 Low level hardware and control layers
6.1 Cryogenic solid state
6.1.1 General
The members of this architecture family have in common that they all make use of a cryostat, where the
quantum devices in a holder are controlled from outside the fridge by room-temperature electronics.
Consequently, a huge amount of control channels is needed to interconnect those two, especially when
many qubits are to be controlled in a single fridge.
The following members have been identified within this architecture family:
— transmons;
— flux qubits;
— semiconductor spin qubits;
— topological qubits;
— artificial atoms in solids.
Four hardware layers have been identified for this architecture family.
6.1.2 Layer 1 – Quantum devices
The quantum devices in the bottom hardware layer function as modules containing qubits, typically
operating at cryogenic temperatures and implemented either as chips or on a PCB. Their quantum states
can be manipulated and read out by sending pulses and measuring their response. These devices may
also have strict requirements regarding shielding, operating temperature, magnetic conditions, and other
environmental factors.
6.1.3 Layer 2 – Control highway
The control highway covers all hardware needed for transporting microwave, lightwave, RF, and DC
signals, via electrical and/or optical means, between the control electronics at room temperature and the
quantum devices at cryogenic temperatures. It is usually a mix of transmission lines, filtering, attenuation,
amplification, (de)multiplexing, as well as means for proper thermalization.
Downstream signals require attenuation at cryogenic temperatures to keep most of the thermal noise
away from the qubits. Overall loss values of 50 dB or more are not uncommon. Additional filtering up to
IR frequencies can reduce unwanted out-of-band noise even further. Since attenuators heat up by
dissipating attenuated signals, they produce more thermal noise than desired. Thermalization is
therefore required to keep attenuators cool and to drain away most of the heat flow from room
temperature nodes through the transmission lines. Superconducting sections can offer additional
thermal isolation to prevent that qubits heat up.
Upstream signals require low-noise amplification, making it essential to minimize signal loss between
the qubit and the first amplifier. When TWPAs (Travelling-Wave Parametric Amplifier) are used as the
first amplification stage, the control highway should transport pump signals as well.
As the number of qubits in a single quantum computer grows rapidly, managing an extensive number of
channels within a single cryostat becomes increasingly complex. The size of a control highway can easily
become very bulky, making it more challenging to keep crosstalk under certain thresholds. Outgassing is
also an issue that is kept minimal since the control highway has to operate under demanding vacuum
conditions. Moreover, it is designed such that vibrations in the cryostat do not induce unwanted signals
into the qubits. Therefore, a control highway is more than just a collection of cables; it is a carefully
designed subsystem essential for efficient operation. A convenient implementation of a control highway
is a module offered as a top or side loader for insertion into a cryostat, having all thermalization on board.
6.1.4 Layer 3 – Control electronics
Hardware layer 3 covers all room temperature electronics for generating, receiving, and processing
microwave, RF, and DC signals. Some implementations make use of routing/switching and/or
multiplexing of control signals. It receives commands from higher layers to fire baseband and modulated
pulses, generate pump signals, and to perform a measurement of qubit responses.
If these commands are standardized, the control electronics can easily be replaced by similar electronics
from other brands. This capability usually requires a simple translation of standardized commands into
proprietary hardware commands for storing samples in the memory of an AWG (Arbitrary Waveform
Generator) or firing a selected pulse.
Figure 1 illustrates that this translation can be accomplished through a thin software wrapper layered
directly above the hardware, serving as an integral component of layer 3. It can be offered as firmware
built into the electronics or as an external piece of (driver) software.
6.1.5 Layer 4 – Control software
6.1.5.1 General
The control software refers to the software systems and tools designed to manage, coordinate and
optimize operations dictated by higher level languages. It plays a crucial role in translating higher-level
quantum assembly instructions into commands that can be handled by the control electronics. This layer
may include an instruction set architecture (ISA), error correction and calibration functionalities (as
shown in Figure 1).
— ISA (Instruction set architecture) refers to a lower-level method of defining operations on a quantum
computer. Instead of defining specific gates, this layer defines gates (or other instructions) as
operations, using pulses pulsed for a certain time, on specific qubits. An example of an instruction set
architecture is pulse level programming where a user can specify wave pulses on qubits instead of
gates. This requires knowledge of the system’s control equipment as well as the topology and qubit
nature.
— Error correction refers to all low-level techniques to enable error-robust physical operations. Error
correction as a whole is a functionality distributed over various (higher) layers. The control software
handles only low-
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