SIST EN IEC 61189-3-302:2026

SLOVENSKI STANDARD
01-marec-2026
Preskusne metode za električne materiale, tiskana vezja in druge povezovalne
strukture in sestave - 3-302. del: Odkrivanje napak pri galvanizaciji golih tiskanih
vezij z računalniško tomografijo (CT)
Test methods for electrical materials, printed board and other interconnection structures
and assemblies - Part 3-302: Detection of plating defects in unpopulated circuit boards
by computed tomography (CT)
Prüfverfahren für Elektromaterialien, Leiterplatten und andere Verbindungsstrukturen
und Baugruppen – Teil 3-302: Computertomographisches Verfahren (CT) zur Detektion
von Metallisierungsfehlern in unbestückten Leiterplatten
Méthodes d’essai pour les matériaux électriques, les cartes imprimées et autres
structures d’interconnexion et ensembles - Partie 3-302: Détection des défauts de
métallisation dans les cartes de circuits imprimés nus par tomographie informatisée (TI)
Ta slovenski standard je istoveten z: EN IEC 61189-3-302:2025
ICS:
31.180 Tiskana vezja (TIV) in tiskane Printed circuits and boards
plošče
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

EUROPEAN STANDARD EN IEC 61189-3-302

NORME EUROPÉENNE
EUROPÄISCHE NORM November 2025
ICS 31.180
English Version
Test methods for electrical materials, printed boards and other
interconnection structures and assemblies - Part 3-302:
Detection of plating defects in unpopulated circuit boards by
computed tomography (CT)
(IEC 61189-3-302:2025)
Méthodes d'essai pour les matériaux électriques, les cartes Prüfverfahren für Elektromaterialien, Leiterplatten und
imprimées et autres structures d'interconnexion et andere Verbindungsstrukturen und Baugruppen - Teil 3-
ensembles - Partie 3-302: Détection des défauts de 302: Computertomographisches Verfahren (CT) zur
métallisation dans les cartes de circuits imprimés nus par Detektion von Metallisierungsfehlern in unbestückten
tomographie informatisée (TI) Leiterplatten
(IEC 61189-3-302:2025) (IEC 61189-3-302:2025)
This European Standard was approved by CENELEC on 2025-11-26. CENELEC members are bound to comply with the CEN/CENELEC
Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration.
Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC
Management Centre or to any CENELEC member.
This European Standard exists in three official versions (English, French, German). A version in any other language made by translation
under the responsibility of a CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the
same status as the official versions.
CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, the Czech Republic,
Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the
Netherlands, Norway, Poland, Portugal, Republic of North Macedonia, Romania, Serbia, Slovakia, Slovenia, Spain, Sweden, Switzerland,
Türkiye and the United Kingdom.

European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung
CEN-CENELEC Management Centre: Rue de la Science 23, B-1040 Brussels
© 2025 CENELEC All rights of exploitation in any form and by any means reserved worldwide for CENELEC Members.
Ref. No. EN IEC 61189-3-302:2025 E

European foreword
The text of document 91/2060/FDIS, future edition 1 of IEC 61189-3-302, prepared by TC 91
"Electronics assembly technology" was submitted to the IEC-CENELEC parallel vote and approved by
CENELEC as EN IEC 61189-3-302:2025.
The following dates are fixed:
• latest date by which the document has to be implemented at national (dop) 2026-11-30
level by publication of an identical national standard or by endorsement
• latest date by which the national standards conflicting with the (dow) 2028-11-30
document have to be withdrawn
Attention is drawn to the possibility that some of the elements of this document may be the subject of
patent rights. CENELEC shall not be held responsible for identifying any or all such patent rights.
Any feedback and questions on this document should be directed to the users’ national committee. A
complete listing of these bodies can be found on the CENELEC website.
Endorsement notice
The text of the International Standard IEC 61189-3-302:2025 was approved by CENELEC as a
European Standard without any modification.
In the official version, for Bibliography, the following note has to be added for the standard indicated:
ISO 15708-1:2024 NOTE Approved as EN ISO 15708-1:2024 (not modified)
Annex ZA
(normative)
Normative references to international publications
with their corresponding European publications
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies. For
undated references, the latest edition of the referenced document (including any amendments)
applies.
NOTE 1  Where an International Publication has been modified by common modifications, indicated by (mod),
the relevant EN/HD applies.
NOTE 2  Up-to-date information on the latest versions of the European Standards listed in this annex is available
here: www.cencenelec.eu.
Publication Year Title EN/HD Year
ISO 15708-3 - Non-destructive testing - Radiation EN ISO 15708-3 -
methods for computed tomography - Part
3: Operation and interpretation

IEC 61189-3-302 ®
Edition 1.0 2025-10
INTERNATIONAL
STANDARD
Test methods for electrical materials, printed boards and other interconnection
structures and assemblies -
Part 3-302: Detection of plating defects in unpopulated circuit boards by
computed tomography (CT)
ICS 31.180  ISBN 978-2-8327-0777-7

IEC 61189-3-302:2025-10(en)
IEC 61189-3-302:2025 © IEC 2025
CONTENTS
FOREWORD . 3
1 Scope . 5
2 Normative references . 5
3 Terms and definitions . 5
4 Test principle . 5
5 Equipment . 6
5.1 X-ray CT scanner . 6
5.1.1 X-ray source system . 6
5.1.2 Mechanical scanning system . 6
5.1.3 Detector system . 6
5.1.4 Shielding facilities . 7
5.2 Software systems . 7
6 Test environment . 7
7 Test the steps . 7
7.1 Equipment preparation . 7
7.2 Sample clamping . 7
7.3 Parameter settings . 8
7.3.1 X-ray sources . 8
7.3.2 Scanning methods . 8
7.3.3 Scanning the field of view . 8
7.3.4 Number of frames scanned . 8
7.3.5 Scan time . 8
7.4 Scanning. 8
7.5 Image reconstruction . 9
7.5.1 3D reconstruction . 9
7.5.2 Image quality . 9
7.5.3 Visualization . 9
7.5.4 Image analysis and data processing . 9
7.5.5 Image saving . 9
8 Reports . 9
8.1 Basic information . 9
8.2 Device information . 9
8.3 Sample information . 9
8.4 Sweep parameters . 10
8.5 Measurement results . 10
Annex A (informative) Typical images of plating defects . 11
A.1 Typical image of plating voids . 11
A.2 Typical image of blind via copper filling defects. 11
A.3 Typical image of nodulation . 12
A.4 Typical image of plating folds . 12
A.5 Typical image of interlayer coincidence . 13
Annex B (informative) Void identification and statistical analysis . 14
B.1 Void identification . 14
B.1.1 Principle . 14
B.1.2 Via . 14
IEC 61189-3-302:2025 © IEC 2025
B.1.3 Fill hole . 15
B.2 Statistical analysis . 15
B.2.1 Number of voids . 15
B.2.2 Calculation of the maximum length of the voids/board thickness ratio . 15
B.2.3 Calculation of filled holes void rate . 16
Bibliography . 17

Figure 1 – Typical process of CT analysis . 5
Figure A.1 – Plating voids . 11
Figure A.2 – Blind via copper filling defects . 12
Figure A.3 – Plating nodulation . 12
Figure A.4 – Plating folds . 13
Figure A.5 – Interlayer coincidence . 13
Figure B.1 – Plating holes voids recognition image . 14
Figure B.2 – Identification of the void along the board thickness direction . 14
Figure B.3 – Fill holes voids recognition image . 15
Figure B.4 – Microvia void image . 15

Table 1 – Reference examples of focal size and spatial resolution correspondence for
source focus size . 6
Table 2 – Reference examples of the imaging resolution of the detector system
corresponding to the imaging field of view . 6

IEC 61189-3-302:2025 © IEC 2025
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
Test methods for electrical materials, printed boards
and other interconnection structures and assemblies -
Part 3-302: Detection of plating defects in unpopulated
circuit boards by computed tomography (CT)

FOREWORD
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IEC 61189-3-302 has been prepared by IEC technical committee 91: Electronics assembly
technology. It is an International Standard.
The text of this International Standard is based on the following documents:
Draft Report on voting
91/2060/FDIS 91/2071/RVD
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this International Standard is English.
IEC 61189-3-302:2025 © IEC 2025
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available
at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
described in greater detail at www.iec.ch/publications.
A list of all parts in the IEC 61189 series, published under the general title Test methods for
electrical materials, printed boards and other interconnection structures and assemblies, can
be found on the IEC w
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