EN IEC 63378-6:2026

SLOVENSKI STANDARD
oSIST prEN IEC 63378-6:2025
01-julij-2025
Standardizacija toplotnih lastnosti pri polprevodniških ohišjih - 6. del: Model
toplotne upornosti in kapacitivnosti za napoved prehodne temperature na spojih
in merilnih točkah
Thermal standardization on semiconductor packages - Part 6: Thermal resistance and
capacitance model for transient temperature prediction at junction and measurement
points
Normalisation thermique des boîtiers de semiconducteurs - Partie 6: Modèle de
résistance thermique et de capacité pour la prédiction de la température transitoire aux
points de jonction et de mesure
Ta slovenski standard je istoveten z: prEN IEC 63378-6:2025
ICS:
31.080.01 Polprevodniški elementi Semiconductor devices in
(naprave) na splošno general
oSIST prEN IEC 63378-6:2025 en
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

oSIST prEN IEC 63378-6:2025
oSIST prEN IEC 63378-6:2025
47D/991/CDV
COMMITTEE DRAFT FOR VOTE (CDV)
PROJECT NUMBER:
IEC 63378-6 ED1
DATE OF CIRCULATION: CLOSING DATE FOR VOTING:
2025-05-23 2025-08-15
SUPERSEDES DOCUMENTS:
47D/969/CD, 47D/990/CC
IEC SC 47D : SEMICONDUCTOR DEVICES PACKAGING
SECRETARIAT: SECRETARY:
Japan Mr Hiroyoshi Yoshida
OF INTEREST TO THE FOLLOWING COMMITTEES: HORIZONTAL FUNCTION(S):
TC 91
ASPECTS CONCERNED:
Digital content,Energy Efficiency
SUBMITTED FOR CENELEC PARALLEL VOTING NOT SUBMITTED FOR CENELEC PARALLEL VOTING
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The attention of IEC National Committees, members of
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for Vote (CDV) is submitted for parallel voting.
The CENELEC members are invited to vote through the
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This document is still under study and subject to change. It should not be used for reference purposes.
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Recipients of this document are invited to submit, with their comments, notification of any relevant “In Some
Countries” clauses to be included should this proposal proceed. Recipients are reminded that the CDV stage is
the final stage for submitting ISC clauses. (SEE AC/22/2007 OR NEW GUIDANCE DOC).

TITLE:
Thermal standardization on semiconductor packages - Part 6: Thermal resistance and
capacitance model for transient temperature prediction at junction and measurement points

PROPOSED STABILITY DATE: 2030
NOTE FROM TC/SC OFFICERS:
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1 CONTENTS
3 FOREWORD . 4
4 INTRODUCTION . 6
5 1 Scope . 7
6 2 Normative references . 7
7 3 Terms and definitions . 7
8 4 Definition of DXRC . 9
9 4.1 General . 9
10 4.2 Thermal Resistance and Capacitance (RC) topology of DXRC . 9
11 4.2.1 Thermal RC topology of DXRC . 9
12 4.2.2 Outline of DXRC . 9
13 4.2.3 RC values on NJA-RC . 10
14 4.2.4 RC values on MPA-RC . 10
15 Annex A (informative) Accuracy Verification of DXRC model for TO-252 . 12
16 A.1 General . 12
17 A.2 CFD Model. 12
18 A.3 Calculation of thermal RC values . 14
19 A.4 MPA-RC and DXRC model outline . 15
20 A.5 Optimization of RC values in MPA-RC . 15
21 A.6 Result . 16
22 Annex B (informative) Accuracy Verification of DXRC model for TO-263 . 18
23 B.1 General . 18
24 B.2 CFD Model. 18
25 B.3 Calculation of thermal RC values . 20
26 B.4 MPA-RC and DXRC model outline . 21
27 B.5 Optimization of RC values in MPA-RC . 21
28 B.6 Result . 22
29 Annex C (informative) Accuracy Verification of DXRC model for HSOP . 23
30 C.1 General . 23
31 C.2 CFD Model. 23
32 C.3 Calculation of thermal RC values . 25
33 C.4 MPA-RC and DXRC model outline . 26
34 C.5 Optimization of RC values in MPA-RC . 26
35 C.6 Result . 27
36 Annex D (informative) The effect of PCB layers . 28
37 D.1 General . 28
38 D.2 Verification Method . 28
39 D.3 Result . 28
40 Bibliography . 30
42 Figure 1 – Thermal RC topology of DXRC . 9
43 Figure 2 – Outline of DXRC . 10
44 Figure A.1 – CFD Model for TO-252 . 12
45 Figure A.2 – Size of TO-252 package . 13

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46 Figure A.3 – Structure Function . 14
47 Figure A.4 – Result of Verification . 17
48 Figure B.1 – CFD Model for TO-263 . 18
49 Figure B.2 – Size of TO-263 package . 19
50 Figure B.2 – Structure Function . 20
51 Figure B.3 – Result of Verification . 22
52 Figure C.1 – CFD Model for HSOP . 23
53 Figure C.2 – Size of HSOP package . 24
54 Figure C.3 – Structure Function . 25
55 Figure C.4 – Result of Verification . 27
56 Figure D.1 – Comparisons of temperature rise between the detailed model and the
57 DXRC model . 29
59 Table A.1 – Material Attributes . 13
60 Table A.2 – Thermal Resistances in NJA-RC . 14
61 Table A.3 – Thermal Capacitances in NJA-RC . 15
62 Table A.4 – Input Variables . 16
63 Table A.5 – Optimized RC values . 16
64 Table B.1 – Material Attributes . 19
65 Table B.2 – Thermal Resistances in NJA-RC . 20
66 Table B.3 – Thermal Capacitances in NJA-RC . 21
67 Table B.4 – Optimized RC values . 22
68 Table C.1 – Material Attributes. 24
69 Table C.2 – Thermal Resistances in NJA-RC . 25
70 Table C.3 – Thermal Capacitances in NJA-RC . 26
71 Table C.4 – Optimized RC values . 27
72 Table D.1 – Combination of the coverages of copper layers . 28
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75 INTERNATIONAL ELECTROTECHNICAL COMMISSION
76 ____________
78 THERMAL STANDARDIZATION ON SEMICONDUCTOR PACKAGES
80 Part 6: Thermal resistance and capacitance model for transient
81 temperature prediction at junction and measurement points
84 INTERNATIONAL ELECTROTECHNICAL COMMISSION
85 ____________
87 FOREWORD
88 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
89 all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international
90 co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and
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96 Standardization (ISO) in accordance with conditions determined by agreement between the two organizations.
97 2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
98 consensus of opinion on the relevant subjects since each technical committee has representation from all
99 interested IEC National Committees.
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114 expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
115 Publications.
116 8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
117 indispensable for the correct application of this publication.
118 9) IEC draws attention to the possibility that the implementation of this document may involve the use of (a)
119 patent(s). IEC takes no position concerning the evidence, validity or applicability of any claimed patent rights in
120 respect thereof. As of the date of publication of this document, IEC had not received notice of (a) patent(s), which
121 may be required to implement this document. However, implementers are cautioned that this may not represent
122 the latest information, which may be obtained from the patent database available at https://patents.iec.ch. IEC
123 shall not be held responsible for identifying any or all such patent rights.
124 IEC 63378-6 has been prepared by subcommittee 47D: Semiconductor devices packaging, of
125 IEC Technical Committee 47: Semiconductor devices. It is an International Standard.

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126 The text of this International Standard is based on the following documents:
Draft Report on voting
47D/XX/FDIS 47D/XX/RVD
128 Full information on the voting for its approval can be found in the report on voting indicated in
129 the above table.
130 The language used for the development of this International Standard is English.
131 This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
132 accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available
133 at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
134 described in greater detail at www.iec.ch/publications.
135 The committee has decided that the contents of this document will remain unchanged until the
136 stability date indicated on the IEC website under webstore.iec.ch in the data related to the
137 specific document. At this date, the document will be
138 • reconfirmed,
139 • withdrawn, or
140 • revised.
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141 INTRODUCTION
142 The IEC 63378-6 series is composed of the following parts:
143 • IEC 63378-6-1 defines the model creation method using a datasheet of semiconductor
144 devices.
145 • IEC 63378-6-2 defines the model creation method using measurement data of
146 semiconductor devices.
147 The IEC 63378-6 series includes subjects such as the definition of a new thermal compact
148 model for thermal transient analysis of semiconductor package, model creation methods,
149 accuracy assessment of these models, etc.
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152 THERMAL STANDARDIZATION ON SEMICONDUCTOR PACKAGES
154 Part 6: Thermal resistance and capacitance model for transient
155 temperature prediction at junction and measurement points
159 1 Scope
160 This part of IEC 63378 specifies a thermal resistance and capacitance model for semiconductor
161 packages. This model is named the Digital Transformation using thermal Resistance and
162 Capacitance (DXRC) model. It predicts transient temperature at junction and measurement
163 points.
164 This document applies to semiconductor packages such as TO-252, TO-263, and HSOP. It
165 supports single chip packages dissipated heat from single package surface.
166 2 Normative references
167 The following documents are referred to in the text in such a way that some or all of their content
168 constitutes requirements of this document. For dated references, only the edition cited applies.
169 For undated references, the latest edition of the referenced document (including any
170 amendments) applies.
171 IEC 60191-2:2012 DB, Mechanical standardization of semiconductor devices - Part 2:
172 Dimensions
173 3 Terms and definitions
174 For the purposes of this document, the following terms and definitions apply.
175 ISO and IEC maintain terminology databases for use in standardization at the following
176 addresses:
177 • IEC Electropedia: available at https://www.electropedia.org/
178 • ISO Online browsing platform: available at https://www.iso.org/obp
180 3.1
181 junction temperature
182 temperature at an arbitrary position of the chip
183 3.2
184 thermal resistance
185 quotient of the difference between the virtual temperature of the device and the temperature of
186 a stated external reference point, by the steady-state power dissipation in the device
187 [SOURCE: IEC 60050-521, 521-05-13]
188 3.3
189 thermal capacitance
190 ability of a material to store thermal energy, calculated by product of specific heat and density

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191 3.4
192 thermal resistance from junction to case top
193 
JC
194 thermal resistance between a junction and a semiconductor package surface
195 3.5
196 Thermal RC topology
197 thermal network consisting of several thermal resistances, capacitances, and nodes
198 3.6
199 T
J
200 thermal node representing the junction in a thermal RC topology
201 3.7
202 
CORE
203 internal thermal node as a branch point, not representing any actual location
204 3.8
205 
N
206 internal thermal nodes between T and T , not representing any actual locations, a natural
J CORE
207 number starting from the one closest to T for N
J
208 3.9
209 T
TOP
210 thermal node representing an arbitrary position on the top surface of the package, with a surface
211 based on the top surface of the package, that exchanges heat with the surrounding environment
212 3.10
213 T
C
214 internal thermal node representing at an arbitrary position on the bottom metal surface of the
215 package
216 3.11
217 T
BI
218 thermal node with a surface based on the metal surface directly under the chip, that exchanges
219 heat with the surrounding environment
220 3.12
221 
BO
222 thermal node with a surface based on the bottom resin surface of the package, that exchanges
223 heat with the surrounding environment
224 3.13
225 
L
226 internal thermal node representing an arbitrary position on the lead terminals
227 3.14
228 
LB
229 thermal node with surfaces based on the bottom surface of the lead terminals, that exchange
230 heat with the surrounding environment
231 3.15
232 
S
233 internal thermal node representing an arbitrary position on a metal heat spreader of the package

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234 3.16
235 
SB
236 thermal node with a surface based on the bottom surface of a part of a metal heat spreader,
237 that exchanges heat with the surrounding environment
239 4 Definition of DXRC
240 4.1 General
241 Compact Thermal Models (CTMs) are commonly used for Computer Fluid Dynamics (CFD)
242 analysis in semiconductor and electronics industries. Using CTMs reduce calculation time and
243 memory usage. However, there are few methods for CTMs which can support transient analysis
244 and estimation of measurement points. DXRC is a method to create CTMs which supports
245 predicting the temperature at a junction and arbitrary measurement points.
246 4.2 Thermal Resistance and Capacitance (RC) topology of DXRC
247 4.2.1 Thermal RC topology of DXRC
248 Thermal RC topology of DXRC shall be defined as Figure 1. It has two RC circuit areas named
249 Near Junction Area – RC (NJA-RC) and Measurement Points Area – RC (MPA-RC). NJA-RC
250 contains a junction node named T and other nodes linking from it named from T to T . These
J 1 N
251 nodes are completely inside nodes, thus they don’t have any surfaces which exchange heat
252 with external environment. Each node has one thermal capacitance and is connected to a
253 neighbouring node. Only T generates heat. The end node of NJA-RC is connected to the top
J
254 node of MPA-RC named T via a thermal resistance. MPA-RC contains three nodes named
CORE
255 T , T and T which are describing measurement points and five nodes named T , T , T ,
C L S BI BO LB
256 T and T which are connecting to external 3D models via CTM surfaces. This topology is
SB TOP
257 defined according to the heat flow paths from junction to package surfaces. Note that this
258 thermal RC topology contains only thermal property inside a package, namely, that about a
259 PCB and other surrounding environments are not contained.
261 Figure 1 – Thermal RC topology of DXRC
262 4.2.2 Outline of DXRC
263 DXRC has T , T , T , T and T as surface nodes. These surfaces should be defined
BI BO LB SB TOP
264 according to outline of semiconductor packages. An example is shown in Figure 2.

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266 Figure 2 – Outline of DXRC
267 4.2.3 RC values on NJA-RC
268 RC values contained NJA-RC shall be calculated by a common method [1]. Measurement,
269 simulation, datasheet of semiconductor packages and any other rising temperature data of
270 junction may be used as input data. The thermal resistance range between T and T should
J N
271 be smaller than between T and T in order to add MPA-RC later.
J C
272 4.2.4 RC values on MPA-RC
273 RC values on MPA-RC shall be optimized to minimize the error defined by equation (1) and (2).
274 Other methods such as curve fitting may be used if equivalent optimization is possible.
275 Additionally, any optimization algorithm may be used. The input data are temperature rises at
276 a junction and at least one measurement point. This temperature data is the same as input data
277 at 4.2.3.
𝑇 (𝑡) − 𝑇 (𝑡)
input DXRC
𝑒_𝑇 (𝑡) = × 100 (1)
J
( )
𝑇 𝑡
input
𝑒_𝑇 (𝑡) = 𝑇 (𝑡) − 𝑇 (𝑡)
(2)
M input DXRC
279 where
280 e_T (t) and e_T (t) are errors at time t between the input data and the result of DXRC for T
J M J
281 and measurement points respectively.
282 T (t) is the temperature of input data.
input
283 T (t) is the estimated temperature by DXRC.
DXRC
284 t in the m-th power of 10 is calculated by equation (3).
1.5
𝑛
𝑚 𝑚+1 𝑚
( ) (3)
𝑡 = 10 + 10 − 10 × ( ) (𝑛 = 1, 2, ⋯ , 10)
287 where
288 m is the integer number.
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290 Both data may be calculated using linear interpolation or other methods if the times of the data don’t
291 correspond to the times defined equation (3). Since error is dependent on surrounding environments
292 such as PCBs, input data should be prepared according to them.

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293 Annex A
294 (informative)
296 Accuracy Verification of DXRC model for TO-252
297 A.1 General
298 The result of
...