IEC TS 62878-2-10:2024
(Main)Device embedding assembly technology - Part 2-10: Design specification for cavity substrate
Device embedding assembly technology - Part 2-10: Design specification for cavity substrate
IEC TS 62878-2-10:2024 provides a general specification for the design of cavity substrates.
General Information
- Status
- Published
- Publication Date
- 30-Jan-2024
- Technical Committee
- TC 91 - Electronics assembly technology
- Drafting Committee
- WG 6 - TC 91/WG 6
- Current Stage
- PPUB - Publication issued
- Start Date
- 31-Jan-2024
- Completion Date
- 16-Feb-2024
Overview
IEC TS 62878-2-10:2024 addresses the design specification for cavity substrates within the context of device embedding assembly technology. Issued by the International Electrotechnical Commission (IEC), this technical specification establishes general guidelines for the design and fabrication of cavity substrates used in advanced electronic packaging.
With the growing adoption of System-in-Package (SiP) technology and continuous demand for reduced package thickness, cavity substrates play a pivotal role in achieving smaller form factors while leveraging proven assembly processes and maintaining cost-efficiency. This standard provides essential reference points for manufacturers, designers, and assembly engineers working with embedded devices and substrates.
Key Topics
- Scope of the Specification:
IEC TS 62878-2-10:2024 provides a comprehensive framework for the design of cavity substrates used in device embedding. - Cavity Formation Methods:
- Milling type: Uses milling for deep cavities.
- Etching type: Employs etching of dielectric materials for isotropic, shallow cavities.
- Laser type: Utilizes laser cutting for precise, shallow cavities.
- Design Elements:
The standard details critical design factors, including:- Top and bottom cavity sizes (A, B)
- Cavity wall to pattern clearances (C)
- Cavity opening to solder resist (SR) and patterns (D, E)
- Cavity taper (F)
- Cavity depth (G)
- System Integration and Miniaturization:
The guidelines support the integration of components in SiP, Wafer-Level Packages (WLP), and Panel-Level Packages (PLP), enabling the creation of compact and high-performance electronic products.
Applications
IEC TS 62878-2-10:2024 benefits a wide range of applications and stakeholders in the electronics industry, particularly where miniaturization and efficient assembly are priorities.
- System-in-Package (SiP):
Cavity substrates are used to reduce the form factor of SiP, enhancing product integration while maintaining reliability and reducing time to market. - Consumer Electronics:
Enables the production of thinner smartphones, tablets, and wearable devices by allowing components to be embedded within the substrate. - Automotive Electronics:
Supports the manufacture of compact and high-reliability modules for advanced driver-assistance systems and infotainment solutions. - Medical Devices:
Allows for the integration of miniaturized, embedded sensors and control electronics in medical instruments. - Industrial Automation:
Facilitates embedded solutions required for robust, space-saving control modules in industrial environments.
By establishing clear design guidelines, this standard helps ensure consistency, manufacturability, and quality across diverse electronics sectors deploying embedded device technology.
Related Standards
For comprehensive implementation and harmonization, the following standards are relevant to users of IEC TS 62878-2-10:2024:
- IEC 60194-2:
Printed boards design, manufacture, and assembly - Vocabulary - Part 2: Common usage in electronic technologies. - IEC 62878 Series:
General device embedding assembly technology standards, offering further information on additional design and process considerations for embedded substrates. - ISO/IEC Directives:
Referenced procedure and guidance documents on international standardization and terminology.
Practical Value
IEC TS 62878-2-10:2024 is crucial for electronics designers, manufacturers, and assembly engineers aiming to optimize embedded component integration. It streamlines the process of reducing product form factor, supports advanced packaging approaches, and ensures international design consistency. By following the specification, stakeholders can accelerate development, reduce risks, and enhance competitiveness in miniaturized electronics markets.
By implementing the design specification for cavity substrates detailed in IEC TS 62878-2-10:2024, organizations can deliver innovative, reliable, and future-ready embedded device solutions.
Frequently Asked Questions
IEC TS 62878-2-10:2024 is a technical specification published by the International Electrotechnical Commission (IEC). Its full title is "Device embedding assembly technology - Part 2-10: Design specification for cavity substrate". This standard covers: IEC TS 62878-2-10:2024 provides a general specification for the design of cavity substrates.
IEC TS 62878-2-10:2024 provides a general specification for the design of cavity substrates.
IEC TS 62878-2-10:2024 is classified under the following ICS (International Classification for Standards) categories: 31.180 - Printed circuits and boards; 31.190 - Electronic component assemblies. The ICS classification helps identify the subject area and facilitates finding related standards.
IEC TS 62878-2-10:2024 is available in PDF format for immediate download after purchase. The document can be added to your cart and obtained through the secure checkout process. Digital delivery ensures instant access to the complete standard document.
Standards Content (Sample)
IEC TS 62878-2-10 ®
Edition 1.0 2024-01
TECHNICAL
SPECIFICATION
colour
inside
Device embedding assembly technology –
Part 2-10: Design specification for cavity substrate
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IEC TS 62878-2-10 ®
Edition 1.0 2024-01
TECHNICAL
SPECIFICATION
colour
inside
Device embedding assembly technology –
Part 2-10: Design specification for cavity substrate
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 31.180; 31.190 ISBN 978-2-8322-8165-9
– 2 – IEC TS 62878-2-10:2024 © IEC 2024
CONTENTS
FOREWORD . 3
1 Scope . 5
2 Normative references . 5
3 Terms and definitions . 5
4 Objective . 5
5 Cavity formation . 5
6 Design guideline . 6
Annex A (informative) Cavity formation examples . 8
A.1 General . 8
A.2 Etching type example . 8
A.3 Laser type example . 9
Figure 1 – Schematic of cavity substate . 6
Figure A.1 – Etching type . 8
Figure A.2 – Laser type . 9
Table 1 – Cavity formation types . 6
Table 2 – Cavity substrate drawing designators . 7
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
DEVICE EMBEDDING ASSEMBLY TECHNOLOGY –
Part 2-10: Design specification for cavity substrate
FOREWORD
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